 English |
|
|
|
|
|
|
|
| HMP8117_07 Datasheet, PDF (13/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder | |||
| |||
| ◁ |
HMP8117
CLK
DVALID
BLANK
P15-P8
Y0
Y1
Y2
Y3
Y4
P7-P0
Cb0
Cr0
Cb2
Cr2
Cb4
NOTES:
tDVLD
9. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate every
cycle due to the 4:2:2 subsampling.
10. BLANK is asserted per Figure 7.
FIGURE 10. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 0)
CLK
DVALID
P15-P11
[P14-P10]
R0
R1
R2
R3
R4
P10-P5
[P9-P5]
G0
G1
G2
G3
G4
P4-P0
B0
B1
B2
B3
B4
NOTE:
tDVLD
11. BLANK is asserted per Figure 7.
FIGURE 11. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0)
13
FN4643.3
April 19, 2007
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese