HMP8117_07 Datasheet, PDF (24/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
BIT
NUMBER
FUNCTION
7
Video Data
Output Enable
6
Video Timing
Output Enable
5
FIELD Polarity
4
BLANK Polarity
3
HSYNC Polarity
2
VSYNC Polarity
1
DVALID Polarity
0
VBIVALID Polarity
TABLE 14. OUTPUT CONTROL REGISTER
SUB ADDRESS = 03_H
DESCRIPTION
This bit is used to enable the P0-P15 outputs.
0 = Outputs 3-stated. 1 = Outputs enabled
This bit is used to enable the HSYNC, VSYNC, BLANK, FIELD, VBIVALID, DVALID, and
INTREQ outputs. 0 = Outputs 3-stated. 1 = Outputs enabled
0 = Active low (low during odd fields). 1 = Active high (high during odd fields)
0 = Active low (low during blanking). 1 = Active high (high during blanking)
0 = Active low (low during horizontal sync). 1 = Active high (high during horizontal sync)
0 = Active low (low during vertical sync). 1 = Active high (high during vertical sync)
0 = Active low (low during valid pixel data). 1 = Active high (high during valid pixel data)
0 = Active low (low during VBI data). 1 = Active high (high during VBI data)
TABLE 15. GENLOCK CONTROL REGISTER
BIT
NO.
FUNCTION
SUB ADDRESS = 04_H
DESCRIPTION
7
Aspect Ratio
Mode
0 = Rectangular (BT.601) pixels
1 = Square pixels
6
Freeze Output
Timing Enable
Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit to a “0”
resumes normal operation at the start of the next field.
0 = Normal operation
1 = Freeze output timing
5
DVALID Duty Cycle This bit is ignored during the 8-bit YCbCr and BT.656 output modes.
Control
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
(DVLD_DCYC)
0 = DVALID has 50/50 duty cycle at the pixel output data rate
1 = DVALID goes active based on line-lock. This will cause DVALID to not have a 50/50 duty
cycle. This bit is intended to be used in maintaining backward compatibility with the HMP8112A
DVALID output timing.
4
DVALID Line Timing During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
Control
0 = DVALID present only during active video time on active scan lines
(DVLD_LTC)
1 = DVALID present the entire scan line time on all scan lines
During the 8-bit YCbCr and BT.656 output modes, this bit defines the DVALID output as:
0 = Normal timing
1 = DVALID signal ANDed with CLK2
3
Missing HSYNC
This bit specifies the number of missing horizontal sync pulses before entering horizontal lock
Detect Select
acquisition mode.
0 = 12 pulses
1 = 1 pulse
2
Missing VSYNC
This bit specifies the number of missing vertical sync pulses before entering vertical lock
Detect Select
acquisition mode.
0 = 3 pulses
1 = 1 pulse
1-0
CLK2 Frequency This bit indicates the frequency of the CLK2 input clock.
00 = 24.54MHz10 = 29.5MHz
01 = 27.0MHz11 = Reserved
RESET
STATE
0_B
0_B
0_B
0_B
0_B
0_B
0_B
0_B
RESET
STATE
0_B
0_B
0_B
0_B
1_B
0_B
01_B
24
FN4643.3
April 19, 2007