HMP8117_07 Datasheet, PDF (21/45 Pages) Intersil Corporation – NTSC/PAL Video Decoder

HMP8117
In order to perform a read from a specific control register
within the HMP8117, an I²C bus write must first be
performed to properly setup the address register. Then an
I²C bus read can be performed to read from the desired
control register(s). As a result of needing the write cycle for a
t_BUF
t_SU:DATA
SDA
t_HD:DATA
read cycle there are actually two START conditions as
shown in Figure 19. The address register is then
auto-incremented after each byte read during the I²C read
cycle. Reserved registers return a value of 00_H.
SCL
t_LOW t_HIGH
t_R t_F
FIGURE 17. I²C TIMING DIAGRAM
tSU:STOP
SDA
SCL
S
1-7
8
9
1-7
8
START
ADDRESS
R/W
CONDITION
ACK
DATA
FIGURE 18. I²C SERIAL DATA FLOW
9
ACK
P
STOP
CONDITION
DATA WRITE
1000 1000
S CHIP ADDR A
0x88
DATA READ _{1000 1000 (R/W)}
S CHIP ADDR A
0x88
SUB ADDR
SUB ADDR
A DATA A DATA A P
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
FROM MASTER
FROM HMP8117
AS
CHIP ADDR
0x89
A DATA A DATA NA P
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
FIGURE 19. REGISTER WRITE/READ FLOW
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
21
FN4643.3
April 19, 2007