82C50A Datasheet, PDF (8/21 Pages) Intersil Corporation – CMOS Asynchronous Communications Element

82C50A
LSR BITS 0 THRU 7
LSR (0) Data Ready (DR)
LSR (1) Overrun Error (OE)
LSR (2) Parity Error (PE)
LSR (3) Framing Error (FE)
LSR (4) Break Interrupt (BI)
LSR (5) Transmitter Holding
Register Empty (THRE)
LSR (6) Transmitter Empty (TEMT)
LSR (7) Not Used
LOGIC 1
Ready
Error
Error
Error
Break
Empty
Empty
LOGIC 0
Not Ready
No Error
No Error
No Error
No Break
Not Empty
Not Empty
The contents of the Line Status Register are indicated in the
above table and are described below.
LSR(0) Data Ready (DR): Data Ready is set high when an
incoming character has been received and transferred into
the Receiver Buffer Register. LSR(0) is reset low by a CPU
read of the data in the Receiver Buffer Register.
LSR(1) Overrun Error (OE): Overrun Error indicates that
data in the Receiver Buffer Register was not read by the
CPU before the next character was transferred into the
Receiver Buffer Register, overwriting the previous character.
The OE indicator is reset whenever the CPU reads the con-
tents of the Line Status Register.
LSR(2) Parity Error (PE): Parity Error indicates that the
received data character does not have the correct even or
odd parity, as selected by the Even Parity Select bit (LCR
(4)). The PE bit is set high upon detection of a parity error,
and is reset low when the CPU reads the contents of the
LSR.
LSR(3) Framing Error (FE): Framing Error indicates that
the received character did not have a valid stop bit. LSR(3) is
set high when the stop bit following the last data bit or parity
bit is detected as a zero bit (spacing level). The FE indicator
is reset low when the CPU reads the contents of the LSR.
LSR(4) Break Interrupt (BI): Break Interrupt is set high
when the received data input is held in the spacing (logic 0)
state for longer than a full word transmission time (start bit +
data bits + parity + stop bits). The B indicator is reset when
the CPU reads the contents of the Line Status Register.
LSR(1) - LSR(4) are the error conditions that produce a
Receiver Line Status interrupt (priority 1 interrupt in the
Interrupt Identification Register (IIR)) when any of the condi-
tions are detected. This interrupt is enabled by setting lER
(2) = 1 in the Interrupt Enable Register.
LSR(5) Transmitter Holding Register Empty
(THRE): THRE indicates that the 82C50A is ready to accept
a new character for transmission. The THRE bit is set high
when a character is transferred from the Transmitter Holding
Register into the Transmitter Shift Register. LSR(5) is reset
low by the loading of the Transmitter Holding Register by the
CPU. LSR(5) is not reset by a CPU read of the LSR.
When the THRE interrupt is enabled (IER(1) = 1), THRE
causes a priority 3 interrupt in the lIR. If THRE is the
interrupt source indicated in IIR, lNTRPT is cleared by a
read of the IIR.
LSR(6) Transmitter Empty (TEMT): TEMT is set high
when the Transmitter Holding Register (THR) and the Trans-
mitter Shift Register (TSR) are both empty. LSR(6) is reset
low when a character is loaded into the THR and remains
low until the character is transferred out of SOUT. TEMT is
not reset low by a CPU read of the LSR.
LSR(7): This bit is permanently set to logic 0.
MODEM CONTROL REGISTER (MCR)
The MCR controls the interface with the modem or data set
as described below. The MCR can be written and read. The
RTS, DTR, OUT1 and OUT2 outputs are directly controlled
by their control bits in this register. A high input asserts a
low (true) at the output pins.
MCR BITS 0 THRU 7
MCR (0) Data Terminal
Ready (DTR)
MCR (1) Request to Send
(RTS)
MCR (2) OUT1
MCR (3) OUT2
MCR (4) LOOP
MCR
MCR
MCR
(5) 0
(6) 0
(7) 0
MCR BIT
LOGIC 1
DTR
Output Low
RTS
Output Low
OUT1
Output Low
OUT2
Output Low
LOOP
Enabled
MCR BIT
LOGIC 0
DTR
Output High
RTS
Output High
OUT1
Output High
OUT2
Output High
LOOP
Disabled
MCR(0): When MCR(0) is set high, the DTR output is forced
low. When MCR(0) is reset low, the DTR output is forced
high. The DTR output of the 82C50A may be input into an
ElA inverting line driver as the 1488 to obtain the proper
polarity input at the modem or data set.
MCR(1): When MCR(1) is set high, the RTS output is forced
low. When MCR(1) is reset low, the RTS output is forced
high. The RTS output of the 82C50A may be input into an
ElA inverting line driver as the 1488 to obtain the proper
polarity input at the modem or data set.
MCR(2): When MCR(2) is set high, the OUT1 output is
forced low. When MCR(2) is reset low, the OUT1 output is
forced high. OUT1 is an user designated output.
MCR(3): When MCR(3) is set high, the OUT2 output is
forced low. When MCR(3) is reset low, the OUT2 output is
forced high. OUT2 is an user designated output.
MCR(4): MCR(4) provides a local loopback feature for diag-
nostic testing of the 62C50A. When MCR(4) is set high,
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