82C50A Datasheet, PDF (5/21 Pages) Intersil Corporation – CMOS Asynchronous Communications Element

82C50A
Pin Description (Continued)
PIN
SYMBOL NUMBER
TYPE
V_CC
40
CS0, CS1, 12,13,
I
CS2
14
I
NC
29
CSOUT
24
O
DDIS
23
O
ADS
25
I
RCLK
9
I
ACTIVE
LEVEL
H
H, H,
L
H
H
L
DESCRIPTION
V_CC: +5V positive power supply pin. A 0.1µA decoupling capacitor from V_CC (pin
40) to GND (pin 20) is recommended.
CHIP SELECT: The Chip Select inputs act as enable signals for the write (DOSTR,
DOSTR) and read (DlSTR, DlSTR) input signals. The Chip Select inputs are latched
by the ADS input.
Do Not Connect
CHIP SELECT OUT: When ACTIVE (high), this pin indicates that the chip has been
selected by active CS0, CS1, and CS2 inputs. No data transfer can be initiated until
CSOUT is a logic 1, ACTIVE (high).
DRIVER DISABLE: This output is INACTIVE (low) when the CPU is reading data
from the 82C50A. An ACTIVE (high) Dells output can be used to disable an external
transceiver when the CPU is reading data.
ADDRESS STROBE: When ACTIVE (low), ADS latches the Register Select (A0,
A1, A2) and Chip Select (CS0, CS1, CS2) inputs. An active ADS is required when
the Register Select pins are not stable for the duration of the read or write operation,
multiplexed mode. If not required, the ADS input should be tied low, non-multiplexed
mode.
This input is the 16X Baud Rate Clock for the receiver section of the 82C50A. This
input may be provided from the BAUDOUT output or an external clock.
Block Diagram
D7 - D0
+5V
GND
A0
A1
A2
CS0
CS1
CS2
ADS
MR
DISTR
DISTR
DOSTR
DOSTR
DDIS
CSOUT
XTAL1
XTAL2
(1 - 8)
(40)
(20)
(28)
(27)
(26)
(12)
(13)
(14)
(25)
(35)
(22)
(21)
(19)
(18)
(23)
(24)
(16)
(17)
DATA BUS
BUFFER
POWER
SUPPLY
SELECT
&
CONTROL
LOGIC
SCRATCH
REGISTER
RECEIVER BUFFER
REGISTER
LINE CONTROL
REGISTER
RECEIVER SHIFT ⁽¹⁰⁾
RECEIVER
RECEIVER TIMING ⁽⁹⁾
& CONTROL
SIN
RCLK
DIVISOR
LATCH (LS)
DIVISOR
LATCH (MS)
BAUD RATE
GENERATOR
(15)
BAUDOUT
LINE STATUS
REGISTER
TRANSMITTER
HOLDING REGISTER
MODEM CONTROL
REGISTER
MODEM STATUS
REGISTER
INTERRUPT ENABLE
REGISTER
INTERRUPT IO
REGISTER
TRANSMITTER
TIMING & CONTROL
TRANSMITTER (11)
SHIFT REGISTER
(32)
(33)
(34)
MODEM
(31)
CONTROL
(36)
LOGIC
(37)
(38)
(39)
SOUT
RTS
DTR
OUT1
OUT2
CTS
DSR
DCD
RI
INTERRUPT
CONTROL
LOGIC
(30)
INTRPT
5