82C50A Datasheet, PDF (21/21 Pages) Intersil Corporation – CMOS Asynchronous Communications Element

82C50A
Timing Waveforms (Continued)
RCLK
SAMPLE CLK
8 CLKS
tSCD (34)
SIN (RECEIVER INPUT DATA)
PARITY
START
DATA BITS (5-8)
STOP
SAMPLE CLK
INTERRUPT
(DATA READY OR RCVR ERR)
DISTR/DISTR
(READ REC DATA BUFFER OR ROLSR)
NOTE 2
NOTES:
1. See Write Cycle Timing.
2. See Read Cycle Timing.
FIGURE 8. RECEIVER TIMING
tSINT (35)
ACTIVE
tRINT
(36)
SERIAL OUT
(SOUT)
INTERRUPT
(THRE)
DOSTR/DOSTR
(WR THR)
NOTE 1
NOTES:
DISTR/DISTR
(RD IIR)
NOTE 2
1. See Write Cycle Timing.
2. See Read Cycle Timing.
START
PARITY
START
(38)
tIRS
(37)
tHR
DATA (5-8)
(37)
tHR
STOP
(1-2)
tSTI (40)
(39)
tSI
FIGURE 9. TRANSMITTER TIMING
tIR (41)
DOSTR/DOSTR (WR MCR)
NOTE 1
RTS, DTR
OUT1, OUT2
ACTIVE
tMDO
(42)
ACTIVE
tMDO
(42)
CTS, DST, DCD
INTERRUPT
(43) tSIM
DISTR/DISTR (RD MSR)
NOTE 2
tRIM
(44)
tSIM
(43)
ACTIVE
RI
NOTES:
1. See Write Cycle Timing.
2. See Read Cycle Timing.
FIGURE 10. MODEM CONTROLS TIMING
tRIM
(44)
tSIM
(43)
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