82C50A Datasheet, PDF (17/21 Pages) Intersil Corporation – CMOS Asynchronous Communications Element

82C50A
AC Electrical Specifications V_CC = 5.0V ±10%, T_A = 0^oC to +70^oC (C82C50A-5)
T_A = -40^oC to +85^oC (l82C50A-5)
T_A = -55^oC to +125^oC (M82C50A-5)
Timing Requirements
82C50A-5
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
(1) TAW Address Strobe Width
50
-
ns
(2) TAS Address Setup Time
60
-
ns
Note 1
(3) TAH Address Hold Time
0
-
ns
(4) TCS Chip Select Setup Time
60
-
ns
Note 1
(5) TCH Chip Select Hold Time
0
-
ns
(6) TDIW DISTR DlSTR Strobe Width
150
-
ns
(7) TRC Read Cycle Delay
270
-
ns
Note 1
(8) RC Read Cycle = TAR + TDIW + TRC
500
-
ns
(9) TDD DISTR DlSTR to Driver Disable Delay
-
75
ns
(10) TDDD Delay From DISTR DlSTR to Data
-
120
ns
(11) THZ DlSTR DISTR to Floating Data Delay
10
75
ns
(12) TDOW DOSTR DOSTR Strobe Width
150
-
ns
(13) TWC Write Cycle Delay
270
-
ns
Note 1
(14) WC Write Cycle = TAW + TDOW + TWC
500
-
ns
(15) TDS Data Setup Time
90
-
ns
(16) TDH Data Hold Time
60
-
ns
NOTE:
1. “When using the 82C50A in the multiplexed mode (ADS operational), it will operate in 80C86/88 systems with a maximum 3MHz operating
frequency.”
AC Electrical Specifications V_CC = 5.0V ±10%, T_A = 0^oC to +70^oC (C82C50A-5)
T_A = -40^oC to +85^oC (l82C50A-5)
T_A = -55^oC to +125^oC (M82C50A-5)
Timing
SYMBOL
PARAMETER
DEMULTIPLEXED OPERATION
(17) TCSC Chip Select Output Delay from Select
(18) TRA Address Hold Time from DISTR DISTR
(19) TRCS Chip Select Hold Time from DISTR DISTR
(20) TAR DISTR DISTR Delay from Address
(21) TCSR DISTR DISTR Delay from Chip Select
(22) TWA Address Hold Time from DOSTR DOSTR
(23) TWCS Chip Select Hold Time from DOSTR DOSTR
(24) TAW DOSTR DOSTR Delay from Address
(25) TCSW DOSTR DOSTR Delay from Select
(26) TMRW Master Reset Pulse Width
(27) TXH Duration of Clock High Pulse
(28) TXL Duration of Clock Low Pulse
82C50A-5
MIN
MAX
-
125
20
-
20
-
80
-
80
-
20
-
20
-
80
-
80
-
500
-
40
-
40
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TEST CONDITIONS
17