82C50A Datasheet, PDF(14/21 Page) Intersil Corporation – CMOS Asynchronous Communications Element

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82C50A Datasheet, PDF (14/21 Pages) Intersil Corporation – CMOS Asynchronous Communications Element

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82C50A

TABLE 5. BAUD RATES USING 2.4576MHz CRYSTAL

DESIRED

BAUD

RATE

110

134.5

150

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

DIVISOR USED TO

GENERATE

16 x CLOCK

3072

2048

1396

1142

1024

512

256

128

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

0.026

0.0007

0.392

0.260

0.775

1.587

TABLE 6. BAUD RATES USING 3.072MHz CRYSTAL

DESIRED

BAUD

RATE

110

134.5

150

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

DIVISOR USED TO

GENERATE

16 x CLOCK

3840

2560

1745

1428

1280

640

320

160

107

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

0.026

0.034

0.312

0.628

1.23

Reset

After powerup, the 82C50A Master Reset Schmitt trigger

input (MR) should be held high for TMRW ns to reset the

82C50A circuits to an idle mode until initialization. A high on

MR causes the following:

1. Initializes the transmitter and receiver internal clock

counters.

2. Clears the Line Status Register (LSR), except for

Transmitter Shift Register Empty (TE MT) and Transmit

Holding Register Empty (THRE), which are set. The

Modem Control Register (MCR) is also cleared. All of the

discrete lines, memory elements and miscellaneous

logic associated with these register bits are also cleared

or turned off. Divisor Latches, Receiver Buffer Register,

Transmitter Buffer Register are not effected.

Following removal of the reset condition (MR low), the

82C50A remains in the idle mode until programmed.

A hardware reset of the 82C50A sets the THRE and TEMT

status bit in the LSR. When interrupts are subsequently

enabled, an interrupt occurs due to THRE.

A summary of the effect of a Master Reset on the 82C50A is

given in Table 7.

Interrupt Enable Register

Interrupt Identification Register

Line Control Register

MODEM Control Register

Line Status Register

MODEM Status Register

SOUT

lntrpt (RCVR Errs)

lntrpt (RCVR Data Ready)

lntrpt (THRE)

lntrpt (Modem Status Changes)

TABLE 7. 82C50A RESET OPERATIONS

RESET CONTROL

Master Reset

Read LSR/MR

Read RBR/MR

Read lIR/Write THR/MR

Read MSR/MR

RESET

All Bits Low (0-3 forced and 4-7 permanent)

Bit 0 is High, Bits 1 and 2 Low Bits 3-7 are

Permanently Low

All Bits Low

All Bits Low, Except Bits 5 and 6 are High

Bit 0-3 Low Bits 4-7 Input Signal

High

Low

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