82C50A Datasheet, PDF (10/21 Pages) Intersil Corporation – CMOS Asynchronous Communications Element

82C50A
the loop mode (MCR(4)=1), MSR(4) is equivalent to RTS in
the MCR.
MSR(5) Data Set Ready (DSR): Data Set Ready (DSR) is a
status of the DSR input (Pin-37) from the modem to the
82C50A which indicates that the modem is ready to provide
received data to the 82C50A receiver circuitry. If the 82C50A
is in the loop mode (MCR(4) = 1), MSR(5) is equivalent to
DTR in the MCR.
MSR(6) Ring Indicator MSR(6): Indicates the status of the
RI input (Pin-39). If the 82C50A is in the loop mode (MCR(4)
= 1), MSR(6) is equivalent to OUT1 in the MCR.
MSR(7) Data Carrier Detect (MSR(7)): Data Carrier Detect
indicates the status of the Data Carrier Detect (DCD) input
(Pin-38). If the 82C50A is in the loop mode (MCR(4) = 1),
MSR(4) is equivalent to OUT2 of the MCR.
The modem status inputs (RI, DCD, DSR and CTS) reflect
the modem input lines with any change of status. Reading
the MSR register will clear the delta modem status indi-
cations but has no effect on the status bits. The status
bits reflect the state of the input pins regardless of the mask
control signals. If a DCTS, DDSR, TERI, or DDCD are true
and a state change occurs during a read operation (DlSTR,
DISTR), the state change is not indicated in the MSR. If
DCTS, DDSR, TERI, or DDCD are false and a state change
occurs during a read operation, the state change is indicated
after the read operation.
For LSR and MSR, the setting of status bits is inhibited
during status register read (DISTR, DlSTR) operations. If a
status condition is generated during a read (DlSTR, DISTR)
operation, the status bit is not set until the trailing edge of the
read (DISTR, DISTR).
If a status bit is set during a read (DlSTR, DISTR) operation,
and the same status condition occurs, that status bit will be
cleared at the trailing edge of the read (DlSTR, DISTR)
instead of being set again.
BAUD RATE SELECT REGISTER (BRSR)
The 82C50A contains a programmable Baud Rate Genera-
tor (BRG) that divides the clock (DC to 10MHz) by any divi-
sor from 1 to 2¹⁶-1 (see also BRG description). The output
frequency of the Baud Generator is 16X the data rate [divisor
# = frequency input ÷ (baud rate x 16)]. Two 8-bit divisor
latch registers store the divisor in a 16-bit binary format.
These Divisor Latch registers must be loaded during initial-
ization. Upon loading either of the Divisor Latches, a 16-bit
Baud counter is immediately loaded. This prevents long
counts on initial load.
Sample Divisor Number Calculation:
Given:
Desired Baud Rate 1200 Baud
Frequency Input 1.8432MHz
Formula: Divisor # = Frequency Input ÷ (Baud Rate x 16)
Divisor # = 1843200 ÷ (1200 x 16)
Answer: Divisor # = 96 = 60_HEX → DLL = 01100000
DLM = 00000000
Check:
The Divisor # 96 will divide the input frequency
1.8432MHz down to 19200 which is 16 times the
desired baud rate.
Divisor Latch Least Significant BYTE
DLL (0)
DLL (1)
DLL (2)
DLL (3)
DLL (4)
DLL (5)
DLL (6)
DLL (7)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Divisor Latch Most Significant BYTE
DLM (0)
DLM (1)
DLM (2)
DLM (3)
DLM (4)
DLM (5)
DLM (6)
DLM (7)
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
RECEIVER BUFFER REGISTER (RBR)
The receiver circuitry in the 82C50A is programmable for 5,
6, 7 or 8 data bits per character. For words of less than 8
bits, the data is right justified to the least significant bit (LSB
= Data Bit 0 (RBR(0)). Data Bit 0 of a data word (RBR(0)) is
the first data bit received. The unused bits in a character less
than 8 bits are output low to the parallel output by the
82C50A.
Received data at the SIN input pin is shifted into the
Receiver Shift Register by the 16X clock provided at the
RCLK input. This clock is synchronized to the incoming data
based on the position of the start bit. When a complete char-
acter is shifted into the Receiver Shift Register, the assem-
bled data bits are parallel loaded into the Receiver Buffer
Register. The DR flag in the LSR register is set.
Double buffering of the received data permits continuous
reception of data without losing received data. While the
Receiver Shift Register is shifting a new character into the
82C50A, the Receiver Buffer Register is holding a previously
received character for the CPU to read. Failure to read the
data in the RBR before complete reception of the next char-
acter result in the loss of the data in the Receiver Register.
The OE flag in the LSR register indicates the overrun condi-
tion.
RBR Bits 0 thru 7
RBR (0)
RBR (1)
RBR (2)
RBR (3)
RBR (4)
RBR (5)
RBR (6)
RBR (7)
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
10