82C50A Datasheet, PDF (4/21 Pages) Intersil Corporation – CMOS Asynchronous Communications Element

82C50A
Pin Description (Continued)
PIN
SYMBOL NUMBER
TYPE
RTS
32
O
BAUDOUT
15
O
OUT1
34
O
OUT2
31
O
RI
39
1
DCD
38
I
MR
35
1
lNTRPT
30
O
SIN
10
I
ACTIVE
LEVEL
DESCRIPTION
L
REQUEST TO SEND: The RTS signal is an output used to enable the modem. The
RTS pin is set low by writing a logic 1 to MCR (1) bit 1 of the Modem Control Regis-
ter. The RTS pin is reset high by Master Reset. When ACTIVE, the RTS pin indicates
to the DCE that the 82C50A has data ready to transmit. In half duplex operations,
RTS is used to control the direction of the line.
BAUDOUT: This output is a 16X clock out used for the transmitter section (16X =
16 times the data rate). The BAUDOUT clock rate is equal to the reference oscillator
frequency divided by the specified divisor in the Baud Rate Generator Divisor Latch-
es DLL and DLM. BAUDOUT may be used by the Receiver section by tying this out-
put to RCLK.
L
OUTPUT 1: This is a general purpose output that can be programmed ACTIVE
(low) by settingVCR(2) (OUT1) of the Modem Control Register to a high level. The
OUT1 pin is set high by Master Reset. The OUT1 pin is INACTIVE (high) during loop
mode operation.
L
OUTPUT 2: This is a general purpose output that can be programmed ACTIVE
(low) by setting MCR(3) (OUT1) of the Modem Control Register to a high level. The
OUT2 pin is set high by Master Reset. The OUT2 signal is INACTIVE (high) during
loop mode operation.
L
RING INDICATOR: When low, RI indicates that a telephone ringing signal has been
received by the modem or data set. The RI signal is a modem control input whose
condition is tested by reading MSR(6) (RI). The Modem Status Register output TERI
(MSR(2)) indicates whether the RI input has changed from a Low to High since the
previous reading of the MSR. If the interrupt is enabled (IER (3) = 1) and RI changes
from a Low to High, an interrupt is generated. The ACTIVE (low) state of RI indicates
that the DCE is receiving a ringing signal. RI will appear ACTIVE for approximately
the same length of time as the ACTIVE segment of the ringing cycle. The INACTIVE
state of RI will occur during the INACTIVE segments not detected by the DCE. This
circuit is not disabled by the INACTIVE condition of DTR.
L
DATA CARRIER DETECT: When ACTIVE (low), DCD indicates that the data carrier
has been detected by the modem or data set. DCD is a modem input whose condi-
tion can be tested by the CPU by reading MSR(7) (DCD) of the Modem Status Reg-
ister. MSR(3) (DDCD) of the Modem Status Register indicates whether the DCD
input has changed since the previous reading of the MSR. DOD has no effect on the
receiver. If the DCD changes state with the modem status interrupt enabled, an in-
terrupt is generated.
When DCD is ACTIVE (low), the received line signal from the remote terminal is
within the limits specified by the DCE manufacturer. The INACTIVE (high) signal in-
dicates that the signal is not within the specified limits, or is not present.
H
MASTER RESET: The MR input forces the 82C50A into an idle mode in which all
serial data activities are suspended. The Modem Control Register (MCR) along with
its associated outputs are cleared. The Line Status Register (LSR) is cleared except
for the THRE and TEMT bits, which are set. The 82C50A remains in an idle state
until programmed to resume serial data activities. The MR input is a Schmitt trigger
input. See the DC Electrical Characteristics for Schmitt trigger logic input voltage
levels. See Table 7 for a summary of Master Reset’s effect on 82C50A operation.
H
INTERRUPT REQUEST: The lNTRPT output goes ACTIVE (high) when one of the
following interrupts has an ACTIVE (high) condition and is enabled by the Interrupt
Enable Register: Receiver Error flag, Received Data Available, Transmitter Holding
Register Empty, and Modem Status. The lNTRPT is reset low upon appropriate ser-
vice or a MR operation. See Figure 1. Interrupt Control Structure.
H
SERIAL DATA INPUT: The SIN input is the serial data input from the communication
line or modem to the 82C50A receiver circuits. A mark (1) is high, and a space (0)
is low. Data inputs on SIN are disabled when operating in the loop mode.
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