X96012_08 Datasheet, PDF (6/23 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look-up Table Memory and DACs

X96012
A/D Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions).
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3) UNIT
NOTES:
[ ] ^{14. LSB” is defined as V(VRef)/255, “Full-Scale” is defined as V(VRef).}
0.5 x V(VRef)
15. Offset_ADC: For an ideal converter, the first transition of its transfer curve occurs at
255
above zero. Offset error is the amount of
[ ] ^{deviation between the measured}
curve occurs at
254.5 x V(VRef)
255
first transition
. Full-Scale
point
Error
and the ideal point. FSError_ADC: For an ideal converter, the last
is the amount of deviation between the measured last transition
transition
point and
of its transfer
the ideal point,
after subtracting the Offset from the measured curve. DNL_ADC: DNL is defined as the difference between the ideal and the measured code
transitions for successive A/D code outputs expressed in LSBs. The measured transfer curve is adjusted for Offset and Full-scale errors before
calculating DNL. INL_ADC: The deviation of the measured transfer function of an A/D converter from the ideal transfer function. The INL error is
also defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured transfer
curve is adjusted for Offset and Full scale errors before calculating INL.
2-Wire Interface AC Characteristics
SYMBOL
f_SCL
t_IN (Note 2)
t_AA (Note 2)
t_BUF (Note 2)
t_LOW
PARAMETER
SCL Clock Frequency
Pulse width Suppression Time at Inputs
SCL Low to SDA Data Out Valid
Time the Bus Free Before Start of New
Transmission
Clock Low Time
TEST CONDITIONS
See “2-Wire Interface Test
Conditions” on page 6
See Figures 1, 2, 3.
t_HIGH
Clock High Time
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_DH
t_R (Note 2)
Start Condition Set-up Time
Start Condition Hold Time
Data In Set-up Time
Data In Hold Time
Stop Condition Set-up Time
Data Output Hold Time
SDA and SCL Rise Time
t_F (Note 2)
SDA and SCL Fall Time
t_SU:WP (Note 2)
t_HD:WP (Note 2)
Cb (Note 2)
WP Set-up Time
WP Hold Time
Capacitive Load for Each Bus Line
MIN
(Note 3)
1
(Note 18)
1300
TYP
MAX
(Note 3)
400
50
900
UNITS
kHz
ns
ns
ns
1.3
0.6
600
600
100
0
600
50
20 +0.1Cb
(Note 16)
20 +0.1Cb
(Note 16)
600
600
1200
µs
(Note 18)
1200
µs
(Note 18)
ns
ns
ns
µs
ns
ns
300
ns
300
ns
ns
ns
400
pF
2-Wire Interface Test Conditions
Input Pulse Levels
Input Rise and Fall Times, between 10% and 90%
Input and Output Timing Threshold Level
External Load at Pin SDA
10% to 90% of V_CC
10ns
1.4V
2.3kΩ to V_CC and 100pF to V_SS
6
FN8216.3
February 20, 2008