X96012_08 Datasheet, PDF (14/23 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look-up Table Memory and DACs

X96012
Look-Up Tables
The X96012 memory array contains two 64-byte look-up
tables. One is associated to pin I1’s output current generator
and the other to pin I2’s output current generator, through
their corresponding D/A converters. The output of each
look-up table is the byte contained in the selected row. By
default these bytes are the inputs to the D/A converters
driving pins I1 and I2.
The byte address of the selected row is obtained by adding
the look-up table base address (90h for LUT1, and D0h for
LUT2) and the appropriate row selection bits. See Figure 9.
By default, the look-up table selection bits are the 6
MSBs of the A/D converter output. Alternatively, the A/D
converter can be bypassed and the six row selection bits
are the six LSBs of Control Registers 1 and 2, for the
LUT1 and LUT2 respectively. The selection between
these options is illustrated in Figure 10, and described in
“I2DS: Current Generator 2 Direction Select Bit (Non-volatile)”
on page 9, and “Control Register 2” on page 10.
Current Generator Block
The Current Generator pins I1 and I2 are outputs of two
independent current mode D/A converters.
D/A Converter Operation
The Block Diagram for each of the D/A converters is shown
in Figure 8.
The input byte of the D/A converter selects a voltage on the
non-inverting input of an operational amplifier. The output of
the amplifier drives the gate of a FET, whose source is
connected to ground via resistor R₁ or R₂. This node is also
fed back to the inverting input of the amplifier. The drain of
the FET is connected to the output current pin (I1 or I2) via a
“polarity select” circuit block.
I1DS OR I2DS: BITS
6 OR 7 IN CONTROL
REGISTER 0.
VCC
POLARITY
SELECT
CIRCUIT
I1 OR I2 PIN
VREF
DAC1 OR
DAC2
INPUT BYTE
VOLTAGE
DIVIDER
+
-
I1FSO[1:0]
OR I2FSO[1:0]
BITS 1 AND 0, OR
3 AND 2 IN CONTROL
REGISTER 5
R1 OR R2 PIN
11
00
10 01
R1_EXTERNAL OR R2_EXTERNAL
OPTIONAL EXTERNAL RESISTOR
VSS
VSS
VSS
VSS
FIGURE 8. D/A CONVERTER BLOCK DIAGRAM
14
FN8216.3
February 20, 2008