X96012_08 Datasheet, PDF (19/23 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look-up Table Memory and DACs

X96012
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte. Refer to Figure 16. This byte includes
three parts:
• The four MSBs (SA7 - SA4) are the Device Type
Identifier, which must always be set to 1010 in order to
select the X96012.
• The next three bits (SA3 - SA1) are the Device Address bits
(AS2 - AS0). To access any part of the X96012’s memory,
the value of bits AS2, AS1, and AS0 must correspond to the
logic levels at pins A2, A1, and A0 respectively.
• The LSB (SA0) is the R/W bit. This bit defines the operation
to be performed on the device being addressed. When the
R/W bit is “1”, then a Read operation is selected. A “0”
selects a Write operation (refer to Figure 16).
BYTE LOAD COMPLETED BY ISSUING
STOP. ENTER ACK POLLING
ISSUE START
ISSUE SLAVE
ADDRESS BYTE
(READ OR WRITE)
ISSUE STOP
NO
ACK RETURNED?
YES
HIGH VOLTAGE
COMPLETE. CONTINUE COMMAND
SEQUENCE.
YES
CONTINUE NORMAL READ OR
WRITE COMMAND SEQUENCE
NO
ISSUE STOP
PROCEED
FIGURE 17. ACKNOWLEDGE POLLING SEQUENCE
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is correctly
issued (including the final STOP condition), the X96012
initiates an internal high voltage write cycle. This cycle
typically requires 5ms. During this time, any Read or Write
command is ignored by the X96012. Write Acknowledge
Polling is used to determine whether a high voltage write
cycle is completed.
During acknowledge polling, the master first issues a START
condition followed by a Slave Address Byte. The Slave
Address Byte contains the X96012’s Device Type Identifier
and Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is busy
within the high voltage cycle, then no ACK is returned. If the
high voltage cycle is completed, an ACK is returned and the
master can then proceed with a new Read or Write
operation. Refer to Figure 17.
Byte Write Operation
In order to perform a Byte Write operation to the memory
array, the Write Enable Latch (WEL) bit of the Control 6
Register must first be set to “1”. See “WEL: Write Enable
Latch (Volatile)” on page 12.
For any Byte Write operation, the X96012 requires the Slave
Address Byte, an Address Byte, and a Data Byte. See
Figure 18. After each of them, the X96012 responds with an
ACK. The master then terminates the transfer by generating a
STOP condition. At this time, if all data bits are volatile, the
X96012 is ready for the next read or write operation. If some
bits are nonvolatile, the X96012 begins the internal write cycle
to the nonvolatile memory. During the internal nonvolatile write
cycle, the X96012 does not respond to any requests from the
master. The SDA output is at high impedance.
A Byte Write operation can access bytes at locations 00h
through FEh directly, when setting the Address Byte to 00h
through FEh respectively. Setting the Address Byte to FFh
accesses the byte at location 100h. The other sixteen bytes,
at locations FFh and 101h through 10Fh can only be
accessed using Page Write operations. The byte at location
FFh can only be written using a “Page Write” operation.
Writing to Control bytes which are located at byte addresses
80h through 8Fh is a special case described in “Writing to
Control Registers” on page 20.
Page Write Operation
The 2176-bit memory array is physically realized as one
contiguous array, organized as 17 pages of 16 bytes each. A
“Page Write” operation can be performed to any of the GPM
or LUT pages. In order to perform a Page Write operation to
the memory array, the Write Enable Latch (WEL) bit in
Control register 6 must first be set See “WEL: Write Enable
Latch (Volatile)” on page 12.
A Page Write operation is initiated in the same manner as
the byte write operation; but instead of terminating the write
cycle after the first data byte is transferred, the master can
transmit up to 16 bytes (see Figure 19). After the receipt of
each byte, the X96012 responds with an ACK, and the
internal byte address counter is incremented by one. The
page address remains constant. When the counter reaches
the end of the page, it “rolls over” and goes back to the first
byte of the same page.
19
FN8216.3
February 20, 2008