X96012_08 Datasheet, PDF (5/23 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look-up Table Memory and DACs

X96012
D/A Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions). (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 3) TYP (Note 3) UNIT
I_OVER
I_UNDER
I1 or I2 Overshoot on D/A Converter Data Byte
Transition
I1 or I2 Undershoot on D/A Converter Data Byte
Transition
DAC input byte changing from 00h to
FFh and vice versa, V(I1) and V(I2)
are V_CC - 1.2V in source mode and
1.2V in sink mode. (Note 2)
0
µA
0
µA
t_rDAC
I1 or I2 Rise Time on D/A Converter Data Byte
Transition; 10% to 90%
5
30
µs
TCO_I1I2
Temperature Coefficient of Output Current I1 or
I2 when Using Internal Resistor Setting
Bits I1FSO[1:0] ¦ 00₂ or
Bits I2FSO[1:0] ¦ 002,
VRMbit = “1”
See Figure 8
±200
ppm/°C
NOTES:
9. DAC input Byte = FFh, Source or sink mode.
[ ] ^{10. LSB is defined as}
2
3
x
V(VRef)
255
divided by the resistance between R₁ or R₂ to V_SS.
11. Offset_DAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed in
LSB. FSError_DAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is
expressed in LSB. The Offset_DAC is subtracted from the measured value before calculating FSError_DAC.DNL_DAC: The Differential Non-Linearity of
a DAC is defined as the deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one
code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNL_DAC. INL_DAC: The
Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the measured transfer
curve for Offset and Full Scale Error. It is expressed in LSB.
12. V(I1) and V(I2) are V_CC - 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies < 1%.
13. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum V_CC = 4.5V. The compliance
voltage changes to 2.5V from the sourcing rail, and the current variation is < 1%.
._{A/D Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions).}
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
ADCTIME
A/D Converter Conversion Time
Proportional to A/D converter input voltage.
This value is maximum at full scale input of
A/D converter. ADCfiltOff = “1”
RIN_ADC
VSense Pin Input Resistance
VSense as an input, ADCIN bit = “1”
100
CIN_ADC
VSense Pin Input Capacitance VSense as an input, ADCIN bit = “1”,
1
Frequency = 1 MHz. (Note 2)
VIN_ADC
VSense Input Signal Range
This is the A/D Converter Dynamic
0
Range. ADCIN bit = “1”
THE ADC IS MONOTONIC
Offset_ADC
A/D Converter Offset Error
(Notes 2, 14)
±1
FSError_ADC A/D Converter Full Scale Error
±1
DNL_ADC
A/D Converter Differential
±0.5
Nonlinearity
INL_ADC
TempStep_ADC
A/D Converter Integral Nonlinearity
Temperature Step Causing One
Step Increment of ADC Output
(Note 2)
±1
0.52
0.55
Out25_ADC
ADC Output at +25°C
01110101₂
MAX
(Note 3)
9
7
V(VRef)
0.58
UNIT
ms
kΩ
pF
V
LSB
LSB
LSB
LSB
°C
5
FN8216.3
February 20, 2008