X96012_08 Datasheet, PDF (18/23 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look-up Table Memory and DACs

X96012
SCL FROM
MASTER
1
SDA OUTPUT FROM
TRANSMITTER
8
9
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 14. ACKNOWLEDGE RESPONSE FROM RECEIVER
X96012 Memory Map
The X96012 contains a 2176 bit array of mixed volatile and
nonvolatile memory. This array is split up into four distinct
parts, namely: (Refer to Figure 15).
• General Purpose Memory (GPM)
• Look-up Table 1 (LUT1)
• Look-up Table 2 (LUT2)
• Control and Status Registers
The GPM is all nonvolatile EEPROM, located at memory
addresses 00h to 7Fh.
ADDRESS
SIZE
10FH
FFH
D0H
CFH
90H
8FH
80H
7FH
00H
7
LOOK-UP TABLE 2
(LUT2)
LOOK-UP TABLE 1
(LUT1)
CONTROL AND STATUS
REGISTERS
GENERAL PURPOSE
MEMORY (GPM)
64 BYTES
64 BYTES
16 BYTES
128 BYTES
0
FIGURE 15. X96012 MEMORY MAP
The Control and Status registers of the X96012 are used in
the test and setup of the device in a system. These registers
are realized as a combination of both volatile and nonvolatile
memory. These registers reside in the memory locations 80h
through 8Fh. The reserved bits within registers 80h through
86h, must be written as “0” if writing to them, and should be
ignored when reading. The reserved registers, from 88h
through 8Fh, must not be written, and their content should
be ignored.
Both look-up tables LUT1 and LUT2 are realized as
non-volatile EEPROM, and extend from memory locations
90h - CFh and D0h - 10Fh respectively. These look-up tables
are dedicated to storing data solely for the purpose of setting
the outputs of Current Generators I1 and I2 respectively.
All bits in both look-up tables are preprogrammed to “0” at the
factory.
Addressing Protocol Overview
All Serial Interface operations must begin with a START,
followed by a Slave Address Byte. The Slave address
selects the X96012, and specifies if a Read or Write
operation is to be performed.
It should be noted that the Write Enable Latch (WEL) bit must
first be set in order to perform a Write operation to any other bit.
See “WEL: Write Enable Latch (Volatile)” on page 12. Also, all
communication to the X96012 over the 2-wire serial bus is
conducted by sending the MSB of each byte of data first.
Even though the 2176 bit memory consists of four differing
functions, it is physically realized as one contiguous array,
organized as 17 pages of 16 bytes each.
The X96012 2-wire protocol provides one address byte,
therefore, only 256 bytes can be addressed directly. The
next few sections explain how to access the different areas
for reading and writing.
SA7 SA6 SA5 SA4 SA3 SA2 SA1 _SA0
1
0
1
0 AS2 AS1 AS0 R/W
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESS
READ OR
WRITE
SLAVE ADDRESS
BIT(S)
DESCRIPTION
SA7 - SA4
Device Type Identifier
SA3 - SA1
Device Address
SA0
Read or Write Operation Select
FIGURE 16. SLAVE ADDRESS (SA) FORMAT
18
FN8216.3
February 20, 2008