X96012_08 Datasheet, PDF (17/23 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look-up Table Memory and DACs

X96012
During all the previous sequence the input of both DACs are
00h. If bit ADCfiltOff is “1”, only one ADC conversion is
necessary. Bits D1DAS, D2DAS, L1DAS, and L2DAS, also
modify the way the two DACs are accessed the first time
after power-up, as described in “Control Register 5” on
page 12.
The X96012 is a hot pluggable device. Voltage disturbances
on the V_CC pin are handled by the power-on reset circuit,
allowing proper operation during hot plug-in applications.
Serial Interface
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. The X96012
operates as a slave in all applications.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are reserved
for indicating START and STOP conditions. See Figure 13.
On power-up of the X96012, the SDA pin is in the input
mode.
Serial Start Condition
All commands are preceded by the START condition, which
is a HIGH to LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command
until this condition has been met. See Figure 12.
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH. The STOP condition is also used to place the
device into the Standby power mode after a read sequence.
A STOP condition can only be issued after the transmitting
device has released the bus. See Figure 12.
Serial Acknowledge
An ACK (Acknowledge), is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the bus after transmitting
eight bits. During the ninth clock cycle, the receiver pulls the
SDA line LOW to acknowledge the reception of the eight bits
of data. See Figure 14.
The device responds with an ACK after recognition of a
START condition followed by a valid Slave Address byte. A
valid Slave Address byte must contain the Device Type
Identifier 1010, and the Device Address bits matching the
logic state of pins A2, A1, and A0. See Figure16.
If a write operation is selected, the device responds with an
ACK after the receipt of each subsequent 8-bit word.
In the read mode, the device transmits eight bits of data,
releases the SDA line, and then monitors the line for an
ACK. The device continues transmitting data if an ACK is
detected. The device terminates further data transmissions if
an ACK is not detected. The master must then issue a STOP
condition to place the device into a known state.
The X96012 acknowledges all incoming data and address
bytes except: 1) The “Slave Address Byte” when the “Device
Identifier” or “Device Address” are wrong; 2) All “Data Bytes”
when the “WEL” bit is “0”, with the exception of a “Data Byte”
addresses to location 86h; 3) “Data Bytes” following a “Data
Byte” addressed to locations 80h, 85h, or 86h.
SCL
SDA
START
STOP
FIGURE 12. VALID START AND STOP CONDITIONS
SCL
SDA
17
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 13. VALID DATA CHANGES ON THE SDA BUS
FN8216.3
February 20, 2008