ISL6308A Datasheet, PDF (6/28 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308A
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Maximum External Reference (Note 4)
REF pin input
-
1.75
-
V
OFS Sink Current Accuracy (Negative Offset)
OFS Source Current Accuracy (Positive Offset)
ERROR AMPLIFIER
R_OFS = 30kΩ from OFS to VCC
R_OFS = 10kΩ from OFS to GND
47.5
50.0
52.5 µA
47.5
50.0
52.5 µA
DC Gain (Note 3)
Gain-Bandwidth Product (Note 3)
Slew Rate (Note 3)
Maximum Output Voltage
R_L = 10k to ground
C_L = 100pF, R_L = 10k to ground
C_L = 100pF, Load = ±400µA
VCC = 5V; Load = 1mA
-
96
-
dB
-
20
-
MHz
-
8
-
V/µs
3.90
4.20
4.60
V
Minimum Output Voltage
Load = -1mA
0.6
0.85
1.0
V
REMOTE SENSE DIFFERENTIAL AMPLIFIER
Input Bias Current (VSEN)
(VSEN = 1.5V)
49
55
60
µA
Bandwidth (Note 3)
-
20
-
MHz
Slew Rate (Note 3)
-
8
-
V/µs
OVERCURRENT PROTECTION
OCSET Trip Current
93
100
107
µA
OCSET Accuracy
OC comparator offset (OCSET and ISUM Difference) -5
0
5
mV
ICOMP Offset
ISEN amplifier offset
-5
0
5
mV
PROTECTION
Undervoltage Threshold
VSEN Falling
80
82
84 %VID
Undervoltage Hysteresis
VSEN Rising - VSEN falling
2
3
4 %VID
Overvoltage Threshold While IC Disabled (V_OVP)
Overvoltage Threshold (V_{OVP_rise})
VSEN Rising
1.62
1.67
1.72
V
DAC + DAC + DAC + V
125mV 150mV 175mV
Overvoltage Hysteresis
VSEN Rising - VSEN Falling
75
100
125 mV
Open Sense-Line Protection Threshold
IREF Rising and Falling
VDIFF VDIFF + VDIFF V
+ 0.9V
1V
+ 1.1V
OVP Output High Drive Voltage
PGOOD Output Low
I_OVP = 50mA, VCC = 5V
VCC = 5V; 1kΩ resistor to VCC
2.2
3.8
4.4
V
0
0.2
0.4
V
SWITCHING TIME
UGATE Rise Time (Note 3)
LGATE Rise Time (Note 3)
UGATE Fall Time (Note 3)
LGATE Fall Time (Note 3)
UGATE Turn-On Non-Overlap (Note 3)
LGATE Turn-On Non-Overlap (Note 3)
GATE DRIVE RESISTANCE (Note 3)
t_RUGATE; V_PVCC = 12V, 3nF Load, 10% to 90%
t_RLGATE; V_PVCC = 12V, 3nF Load, 10% to 90%
t_FUGATE; V_PVCC = 12V, 3nF Load, 90% to 10%
t_FLGATE; V_PVCC = 12V, 3nF Load, 90% to 10%
t_PDHUGATE; V_PVCC = 12V, 3nF Load, Adaptive
t_PDHLGATE; V_PVCC = 12V, 3nF Load, Adaptive
-
26
-
ns
-
18
-
ns
-
18
-
ns
-
12
-
ns
-
10
-
ns
-
10
-
ns
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
V_PVCC = 12V, 150mA Source Current
V_PVCC = 12V, 150mA Sink Current
V_PVCC = 12V, 150mA Source Current
1.25
2.0
0.9
1.6
0.85
1.4
3.0
Ω
3.0
Ω
2.2
Ω
6
FN6669.0
September 9, 2008