ISL6308A Datasheet, PDF (19/28 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308A
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t₂. In Equation 17, the
approximate power loss is P_UP,2.
P_{UP, 2}
≈
V_IN
⋅
⎛
⎜
-I-^M---
⎝^N
–
I--_{P----P--⎟⎞}
2_⎠
⋅
⎛
⎜
t--_2--
⎞
⎟
⎝ ²âŽ 
⋅
F_SW
(EQ. 17)
A third component involves the lower MOSFET
reverse-recovery charge, Q_rr. Since the inductor current has
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q_rr, it is
conducted through the upper MOSFET across V_IN. The
power dissipated as a result is P_UP,3.
P_UP,3 = V_IN ⋅ Q_rr ⋅ F_SW
(EQ. 18)
Finally, the resistive part of the upper MOSFET is given in
Equation 19 as P_UP,4.
P_UP,4 ≈ r_DS(ON) ⋅ d ⋅
⎛
⎜
⎝
I--_{M---⎟⎞}
N⎠
2
+
-I-^P----^P--²-
12
(EQ. 19)
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 16, 17, 18 and 19. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 6x6 QFN package is approximately 4W at
room temperature. See “Layout Considerations” on page 25
for thermal transfer improvement suggestions.
When designing the ISL6308A into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P_{Qg_TOT}, due to the gate charge of MOSFETs and the
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 20
and 21, respectively.
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q ⋅ VCC
(EQ. 20)
P _{Q g _Q1}
=
3_--
2
⋅
Q_G
1
⋅
P
V
C
C
⋅
F_SW
⋅
N_Q1
⋅
N_P
H
A
S
E
P_{Qg_Q2} = Q_G2 ⋅ PVCC ⋅ F_SW ⋅ N_Q2 ⋅ N_PHASE
I_DR
=
⎛
⎝
3_--
2
•
Q_G
1
•
N_Q
1
+
Q_G
2
•
N_{Q2⎠⎞}
• N_PHASE • F_SW + I_Q
(EQ. 21)
In Equations 20 and 21, P_{Qg_Q1} is the total upper gate drive
power loss and P_{Qg_Q2} is the total lower gate drive power
loss; the gate charge (Q_G1 and Q_G2) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I_Q is the driver total
quiescent current with no load at both drive outputs; N_Q1
and N_Q2 are the number of upper and lower MOSFETs per
phase, respectively; N_PHASE is the number of active
phases. The I_Q*VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
300kHz.
PVCC
BOOT
D
R_HI1
R_LO1
UGATE
C_GD
G
R_G1
R_GI1
C_GS
S
C_DS
Q1
PHASE
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R_HI2
R_LO2
LGATE
C_GD
G
R_G2
R_GI2
C_GS
S
D
C_DS
Q2
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
19
FN6669.0
September 9, 2008