ISL6308A Datasheet, PDF (18/28 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308A
Overtemperature Protection
The ISL6308A constantly monitors the temperature of the
die. If it exceeds the Thermal Shutdown Setpoint
(thermal_set), both the controller and the output drivers will be
disabled, shutting down the output. Once the die
temperature cools to the Thermal Recovery Setpoint
(thermal_rec), the ISL6308A will go through an initialization
and soft-start, and attempt to resume normal operation. The
timing of the on/off cycles depends on the ambient
temperature, the thermal mounting of the IC package and
the FETs on the board, airflow, and other thermal
considerations.
Note that both trip points (nominal 160°C and 135°C) are
well beyond the maximum ambient temperature, over which
the specifications are guaranteed. Running continuously
above the rated temperature can degrade the life of the IC.
The OTP circuit is designed to protect the IC and system
from an occasional excursion; it should not be allowed as
part of normal operation or testing.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following. In addition to this guide, Intersil provides complete
reference designs that include schematics, bills of materials,
and example board layouts for many applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount
designs will tend toward the lower end of this current range.
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and heat
dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for the approximate power loss in the lower
MOSFET can be simplified, since virtually all of the loss in
the lower MOSFET is due to current conducted through the
channel resistance (r_DS(ON)). In Equation 14, I_M is the
maximum continuous output current, I_PP is the peak-to-peak
inductor current (see Equation 1), and d is the duty cycle
(V_OUT/V_IN).
P_{LOW, 1}
=
r_D
S
·
(O
N
)
⋅
⎛
⎜
⎝
-I-^M---⎟⎞
N⎠
2
⋅
(
1
–
d
)
+
I--_L---,---^2P_----P-----⋅_---(_--1-----–_-----d----)
12
(EQ. 14)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I_M, V_D(ON), the switching
frequency, F_SW, and the length of dead times, t_d1 and t_d2, at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
P_{LOW, 2} = V_D(ON) ⋅ F_SW ⋅
⎛
⎝
-I-^M---
N
+
-I-^P--2--^P--_⎠⎞
⋅
t_d1
+
⎛
⎝
-I-^M---
N
–
I--_{P-2---P--⎠⎞}
⋅
t_d2
(EQ. 15)
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P_LOW,1 and P_LOW,2.
UPPER MOSFET POWER CALCULATION
In addition to r_DS(ON) losses, a large portion of the upper
MOSFET losses are due to currents conducted across the
input voltage (V_IN) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode reverse
recovery charge, Q_rr, and the upper MOSFET r_DS(ON)
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 16,
the required time for this commutation is t₁ and the
approximated associated power loss is P_UP,1.
P_UP,1 ≈ V_IN
⋅
⎛
⎝
I--_M---
N
+ ^I--P-2---^P--_⎠⎞
⋅
⎛
⎜
t--_1--
⎞
⎟
⎝ ²âŽ 
⋅ F_SW
(EQ. 16)
18
FN6669.0
September 9, 2008