ISL6308A Datasheet, PDF (14/28 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308A
By simply adjusting the value of R_S, the load line can be set to
any level, giving the converter the right amount of droop at all
load currents. It may also be necessary to compensate for any
changes in DCR due to temperature. These changes cause
the load line to be skewed, and cause the R-C time constant
to not match the L/DCR time constant. If this becomes a
problem a simple negative temperature coefficient resistor
network can be used in the place of R_COMP to compensate
for the rise in DCR due to temperature.
Output Voltage Offset Programming
The ISL6308A allows the designer to accurately adjust the
offset voltage by connecting a resistor, R_OFS, from the OFS
pin to VCC or GND. When R_OFS is connected between OFS
and VCC, the voltage across it is regulated to 1.5V. This
causes a proportional current (I_OFS) to flow into the OFS pin
and out of the FB pin. If R_OFS is connected to ground, the
voltage across it is regulated to 0.5V, and I_OFS flows into the
FB pin and out of the OFS pin. The offset current flowing
through the resistor between VDIFF and FB will generate
the desired offset voltage which is equal to the product
(I_OFS x R₁). These functions are shown in Figures 8 and 9.
Once the desired output offset voltage has been determined,
use the following formulas to set R_OFS:
For Positive Offset (connect R_OFS to GND):
R_OFS
=
----⁰---^.--⁵-----^â‹---^R----¹-----
V_OFFSET
(EQ. 9)
For Negative Offset (connect R_OFS to VCC):
R_OFS
=
----¹---^.--⁵-----^â‹---^R----¹-----
V_OFFSET
(EQ. 10)
VDIFF
+
V_{OFS R1}
-
VREF
E/A
FB
I_OFS
R_OFS
OFS
ISL6308A
GND
+
0.5V
-
-
1.5V
+
GND
VCC
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VDIFF
-
V_{OFS R1}
+
VREF
E/A
FB
I_OFS
VCC
R_OFS
OFS
ISL6308A
+
0.5V
-
-
1.5V
+
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive
deadtime control technique to minimize deadtime, resulting
in high efficiency from the reduced freewheeling time of the
lower MOSFET body-diode conduction, and to prevent the
upper and lower MOSFETs from conducting simultaneously.
This is accomplished by ensuring either rising gate turns on
its MOSFET with minimum and sufficient delay after the
other has turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is
released to rise. An auto-zero comparator is used to correct
the r_DS(ON) drop in the phase voltage preventing false
detection of the -0.3V phase level during r_DS(ON) conduction
period. In the case of zero current, the UGATE is released
after 35ns delay of the LGATE dropping below 0.5V. During
the phase detection, the disturbance of LGATE falling
transition on the PHASE node is blanked out to prevent
falsely tripping. Once the PHASE is high, the advanced
adaptive shoot-through circuitry monitors the PHASE and
UGATE voltages during a PWM falling edge and the
subsequent UGATE turn-off. If either the UGATE falls to less
than 1.75V above the PHASE or the PHASE falls to less than
+0.8V, the LGATE is released to turn on.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
14
FN6669.0
September 9, 2008