ISL6308A Datasheet, PDF (22/28 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308A
Case 3:
F₀
>
----------------1-----------------
2π ⋅ C ⋅ ESR
R₂
=
R₁
⋅
2----π_------⋅_{---F----0----}⋅_{---V----O-----S----C-----}⋅_---L--
0.66 ⋅ V_IN ⋅ ESR
C₂
=
----0---.--6---6-----^â‹---V----^I--^N-----^â‹---E-----S----R------^â‹-------C------
2π ⋅ V_OSC ⋅ R₁ ⋅ F₀ ⋅ L
In Equations 28, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent series
resistance of the bulk output filter capacitance; and V_PP is
the peak-to-peak sawtooth signal amplitude, as described in
the “Electrical Specifications” table.
Once selected, the compensation values in Equations 28
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R₂. Slowly increase the
value of R₂ while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C₁ will not need adjustment. Keep the value of C₁ from
Equations 28 unless some performance issue is noted.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 19). Keep
a position available for C₂, and be prepared to install a high
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
Compensating the Converter Operating Without
Load-Line Regulation
The ISL6308A multi-phase converter operating without load
line regulation behaves in a similar manner to a voltage-
mode controller. This section highlights the design
consideration for a voltage-mode controller requiring external
compensation. To address a broad range of applications, a
type-3 feedback network is recommended (see Figure 20).
C₂
R₂
C₁
COMP
C₃
R₁
R₃
FB
VDIFF
ISL6308A
FIGURE 20. COMPENSATION CONFIGURATION FOR
NON-LOAD-LINE REGULATED ISL6308A
Figure 21 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable, with a
small number of adjustments, to the multi-phase ISL6308A
circuit. The output voltage (V_OUT) is regulated to the reference
voltage, VREF, level. The error amplifier output (COMP pin
voltage) is compared with the oscillator (OSC) modified saw-
tooth wave to provide a pulse-width modulated wave with an
amplitude of V_IN at the PHASE node. The PWM wave is
smoothed by the output filter (L and C). The output filter
capacitor bank’s equivalent series resistance is represented by
the series resistor E.
C₂
COMP
R₂
C₁
-
FB
E/A ⁺
VREF
R₃
C₃
R₁
VDIFF
-
RGND
+
VSEN
PWM
CIRCUIT
OSCILLATOR
V_OSC
HALF-BRIDGE
DRIVE
V_OUT
V_IN
UGATE
PHASE
L
DCR
C
LGATE
ESR
ISL6308A EXTERNAL CIRCUIT
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of V_OUT/V_COMP. This function is dominated by a DC
gain, given by d_MAXV_IN/V_OSC, and shaped by the output
filter, with a double pole break frequency at F_LC and a zero at
F_CE. For the purpose of this analysis, L and DCR represent
the individual channel inductance and its DCR divided by 3
(equivalent parallel value of the three output inductors), while
C and ESR represents the total output capacitance and its
equivalent series resistance.
F_LC=
-------------¹--------------
2π ⋅ L ⋅ C
F_CE= ₂----_π-----_â‹---_C----¹--_â‹---_E----_S-----_R---
(EQ. 29)
The compensation network consists of the error amplifier
(internal to the ISL6308A) and the external R₁-R₃, C₁-C₃
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F₀; typically 0.1 to 0.3 of F_SW) and adequate phase
22
FN6669.0
September 9, 2008