ISL6308A Datasheet, PDF (23/28 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308A
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F_0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R₁, R₂, R₃, C₁, C₂, and
C₃) in Figure 20 and 21. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R₁ (1kΩ to 5kΩ, typically). Calculate
value for R₂ for desired converter bandwidth (F₀).
R₂ = -_d--^V-_M----^O-_A---^S-_X---^C--_â‹---_V^â‹---^R-_I--_N--¹---_â‹-^â‹--_F-^F---_L-⁰--_C---
(EQ. 30)
If setting the output voltage to be equal to the reference
set voltage as shown in Figure 21, the design procedure
can be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
to compensate for the attenuation introduced by the
resistor divider, the obtained R₂ value needs be
multiplied by a factor of (R_P + R_S)/R_P. The remainder of
the calculations remain unchanged, as long as the
compensated R₂ value is used.
2. Calculate C₁ such that F_Z1 is placed at a fraction of the F_LC,
at 0.1 to 0.75 of F_LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F_CE/F_LC, the lower the F_Z1
frequency (to maximize phase boost at F_LC).
C₁ = -₂---_π-----_â‹---_R-----₂----_â‹--¹-₀---_.--₅-----_â‹---_F----_L---_C--
(EQ. 31)
3. Calculate C₂ such that F_P1 is placed at F_CE.
C₂
=
-------------------------^C-----¹-------------------------
2π ⋅ R₂ ⋅ C₁ ⋅ F_CE – 1
(EQ. 32)
4. Calculate R₃ such that F_Z2 is placed at F_LC. Calculate C₃
such that F_P2 is placed below F_SW (typically, 0.5 to 1.0
times F_SW). F_SW represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F_P2 lower in
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
R₃
=
--------^R-----¹--------
F_{----S----W----}
F_LC
–
1
(EQ. 33)
C₃
=
-----------------------¹-------------------------
2π ⋅ R₃ ⋅ 0.7 ⋅ F_SW
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G_MOD), feedback
compensation (G_FB) and closed-loop response (G_CL):
G_MOD(f)
=
-^d---^M-----^A----^X-----^â‹---^V----^I--^N-- ⋅ -------------------------------¹-----+-----^s---⁽---^f--⁾---^â‹---^E-----^S----^R------^â‹---^C----------------------------------
V_{OSC 1 + s(f) ⋅ (ESR + DCR) ⋅ C + s}2_{(f) ⋅ L ⋅ C}
G_FB(f)
=
-----¹-----+-----^s---⁽---^f--⁾---^â‹---^R-----²----^â‹---^C-----¹------
s(f) ⋅ R₁ ⋅ (C₁ + C₂)
⋅
(EQ. 34)
⋅ ------------------------------¹-----+-----^s---⁽---^f--⁾---^â‹---⁽---^R----¹-----+-----^R----³----⁾---^â‹---^C-----³-------------------------------
(1
+
s
(
f
)
⋅
R₃
⋅
C₃
)
⋅
⎛
⎜1
⎝
+
s
(
f
)
⋅
R₂
⋅
⎛
⎜
⎝
C^-C----₁^{-1----+-⋅--C-}C^----2-₂^-_{⎠⎟⎞}
⎞
⎟
⎠
G_CL(f) = G_MOD(f) ⋅ G_FB(f) _{where, s(f) = 2π ⋅ f ⋅ j}
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1 = ₂----_π-----_â‹---_R--¹---₂----_â‹---_C-----₁-
(EQ. 38)
F_Z2 = ₂----_π-----_â‹---₍---_R----₁----+-¹----_R-----₃---₎----_â‹---_C----₃--
F_P1
=
---------------------¹-----------------------
2
π
⋅
R₂
⋅
-^C-----¹----^â‹---^C-----²--
C₁ + C₂
(EQ. 35)
(EQ. 36)
F_P2
=
--------------¹----------------
2π ⋅ R₃ ⋅ C₃
(EQ. 37)
Figure 22 shows an asymptotic plot of the DC/DC
converter’s gain vs frequency. The actual Modulator Gain
has a high gain peak dependent on the quality factor (Q) of
the output filter, which is not shown. Using the above
guidelines should yield a compensation gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F_P2
against the capabilities of the error amplifier. The closed loop
gain, G_CL, is constructed on the log-log graph of Figure 22
by adding the modulator gain, G_MOD (in dB), to the feedback
compensation gain, G_FB (in dB). This is equivalent to
multiplying the modulator transfer function and the
compensation transfer function and then plotting the
resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin. The mathematical model
presented makes a number of approximations and is
generally not accurate at frequencies approaching or
exceeding half the switching frequency. When designing
compensation networks, select target crossover frequencies
in the range of 10% to 30% of the per-channel switching
frequency, F_SW.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
23
FN6669.0
September 9, 2008