ISL6308A Datasheet, PDF (16/28 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308A
to regulate to zero volts at the beginning of the soft-start
cycle. The Output soft-start time, t_SS, begins with a delay
period equal to 64 switching cycles after the ENLL has
exceeded its POR level, followed by a linear ramp with a rate
determined by the switching period, 1/F_sw.
t_SS
=
6_----4_-----+-----D_----A_-----C_------⋅_---1_---2_---8_----0_-
F_SW
(EQ. 12)
For example, a regulator with 450kHz switching frequency
having REF voltage set to 1.2V has t_SS equal to 3.55ms.
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft-start and ramps to zero during the first 640
cycles of soft-start (704 cycles following enable). This
prevents the large inrush current that would otherwise occur
should the output voltage start out with a slight negative bias.
The ISL6308A also has the ability to start up into a
pre-charged output as shown in Figure 12, without causing
any unnecessary disturbance. The FB pin is monitored
during soft-start, and should it be higher than the equivalent
internal ramping reference voltage, the output drives hold
both MOSFETs off. Once the internal ramping reference
exceeds the FB pin potential, the output drives are enabled,
allowing the output to ramp from the pre-charged level to the
final level dictated by the reference setting. Should the
output be pre-charged to a level exceeding the reference
setting, the output drives are enabled at the end of the soft-
start period, leading to an abrupt correction in the output
voltage down to the “reference set” level.
Fault Monitoring and Protection
The ISL6308A actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to the load.
One common power good indicator is provided for linking to
external system monitors. The schematic in Figure 13
outlines the interaction between the fault monitors and the
power-good signal.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
GND>
V_OUT (0.5V/DIV)
GND>
ENLL (5V/DIV)
T1 T2
T3
FIGURE 12. SOFT-START WAVEFORMS FOR ISL6308A-
BASED MULTI-PHASE CONVERTER
*CONNECT DROOP TO IREF
TO DISABLE THE DROOP FEATURE.
R_OCSET
IREF
ISUM
DROOP* _{ICOMP - VOCSET +}
+
ISEN
-
-
V_DROOP
+
OCSET
100µA
VDIFF
+
OC
+1V
-
DAC + 150mV
V_OVP
VSEN
RGND
+
x1
-
SOFT-START, FAULT
AND CONTROL LOGIC
-
OV
+
-
UV
+
PGOOD
0.82 x DAC _{ISL6308A INTERNAL CIRCUITRY}
FIGURE 13. POWER-GOOD AND PROTECTION CIRCUITRY
Power-Good Signal
The power-good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft-start. PGOOD pulls low during shutdown and releases
high after a successful soft-start. PGOOD transitions low
when an undervoltage, overvoltage, or overcurrent condition
is detected or when the controller is disabled by a reset from
ENLL or POR. If after an undervoltage or overvoltage event
occurs the output returns to within under and overvoltage
limits, PGOOD will return high.
Undervoltage Detection
The undervoltage threshold is set at 82% of the REF
voltage. When the output voltage (VSEN-RGND) is below
the undervoltage threshold, PGOOD gets pulled low. No
other action is taken by the controller. PGOOD will return
high if the output voltage rises above 85% of the REF
voltage.
Overvoltage Protection
Actions are taken by the ISL6308A to protect the load when
an overvoltage condition occurs, until the output voltage falls
back within set limits.
16
FN6669.0
September 9, 2008