ISL6308A Datasheet, PDF (10/28 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

ISL6308A
I_L1 + I_L2 + I_L3, 7A/DIV
I_L3, 7A/DIV
PWM3, 5V/DIV
I_L2, 7A/DIV
PWM2, 5V/DIV
I_L1, 7A/DIV
PWM1, 5V/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine Equation 1, which represents
an individual channel peak-to-peak inductor current.
I_{PP =}
(_{---V----I--N-----}–_{-----V----O-----U----T---})_----⋅_{----V----O----U-----T-}
L ⋅ F_SW ⋅ V_IN
(EQ. 1)
In Equation 1, V_IN and V_OUT are the input and output
voltages respectively, L is the single-channel inductor value,
and F_SW is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
I_{C, PP}=
(_{---V----I--N-----}–_-----N------⋅_{----V----O-----U----T----})_---⋅_{----V----O----U-----T-}
L ⋅ F_SW ⋅ V_IN
(EQ. 2)
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 6.1A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has a 13.3A
RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
10
INPUT-CAPACITOR CURRENT
CHANNEL 3
INPUT CURRENT
CHANNEL 2
INPUT CURRENT
CHANNEL 1
INPUT CURRENT
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
Figures 24, 25 and 26 in the section entitled “Input Capacitor
Selection” on page 25 can be used to determine the input
capacitor RMS current based on load current, duty cycle,
and the number of channels. They are provided as aids in
determining the optimal input capacitor solution.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the
ISL6308A is three. One switching cycle is defined as the
time between the internal PWM1 pulse termination signals.
The pulse termination signal is the internally generated clock
signal that triggers the falling edge of PWM1. The cycle time
of the pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
PWM1 to go low. The PWM1 transition signals the internal
channel 1 MOSFET driver to turn off the channel 1 upper
MOSFET and turn on the channel 1 synchronous MOSFET.
In the default channel configuration, the PWM2 pulse
terminates 1/3 of a cycle after the PWM1 pulse. The PWM3
pulse terminates 1/3 of a cycle after PWM2.
If PVCC3 is left open or connected to ground, two channel
operation is selected and the PWM2 pulse terminates 1/2 of
a cycle after the PWM1 pulse terminates. If both PVCC3 and
PVCC2 are left open or connected to ground, single channel
operation is selected. The 2PH and 3PH inputs can also be
used to accomplish this function. Once a PWM pulse
transitions low, it is held low for a minimum of 1/3 cycle. This
forced off time is required to ensure an accurate current
sample. Current sensing is described in the next section.
After the forced off time expires, the PWM output is enabled.
The PWM output state is driven by the position of the error
amplifier output signal, VCOMP, minus the current correction
signal relative to the sawtooth ramp as illustrated in Figure 3.
When the modified VCOMP voltage crosses the sawtooth
ramp, the PWM output transitions high. The internal
FN6669.0
September 9, 2008