8259A Datasheet, PDF (9/24 Pages) Intel Corporation – PROGRAMMABLE INTERRUPT CONTROLLER

8259A
Content of Second Interrupt Vector Byte
IR
Interval ^e 4
D7 D6 D5 D4 D3 D2 D1 D0
7 A7 A6 A5 1 1 1 0 0
6 A7 A6 A5 1 1 0 0 0
5 A7 A6 A5 1 0 1 0 0
4 A7 A6 A5 1 0 0 0 0
3 A7 A6 A5 0 1 1 0 0
2 A7 A6 A5 0 1 0 0 0
1 A7 A6 A5 0 0 1 0 0
0 A7 A6 A5 0 0 0 0 0
IR
Interval ^e 8
D7 D6 D5 D4 D3 D2 D1 D0
7 A7 A6 1 1 1 0 0 0
6 A7 A6 1 1 0 0 0 0
5 A7 A6 1 0 1 0 0 0
4 A7 A6 1 0 0 0 0 0
3 A7 A6 0 1 1 0 0 0
2 A7 A6 0 1 0 0 0 0
1 A7 A6 0 0 1 0 0 0
0 A7 A6 0 0 0 0 0 0
During the third INTA pulse the higher address of the
appropriate service routine which was programmed
as byte 2 of the initialization sequence (A₈ – A₁₅) is
enabled onto the bus
Content of Third Interrupt Vector Byte
D7 D6 D5 D4 D3 D2 D1 D0
A15 A14 A13 A12 A11 A10 A9 A8
composed as follows (note the state of the ADI
mode control is ignored and A₅ – A₁₁ are unused in
8086 mode)
Content of Interrupt Vector Byte
for 8086 System Mode
D7 D6 D5 D4 D3 D2 D1 D0
IR7 T7 T6 T5 T4 T3 1 1 1
IR6 T7 T6 T5 T4 T3 1 1 0
IR5 T7 T6 T5 T4 T3 1 0 1
IR4 T7 T6 T5 T4 T3 1 0 0
IR3 T7 T6 T5 T4 T3 0 1 1
IR2 T7 T6 T5 T4 T3 0 1 0
IR1 T7 T6 T5 T4 T3 0 0 1
IR0 T7 T6 T5 T4 T3 0 0 0
PROGRAMMING THE 8259A
The 8259A accepts two types of command words
generated by the CPU
1 Initialization Command Words (ICWs) Before
normal operation can begin each 8259A in the
system must be brought to a starting point by a
sequence of 2 to 4 bytes timed by WR pulses
2 Operation Command Words (OCWs) These are
the command words which command the 8259A
to operate in various interrupt modes These
modes are
a Fully nested mode
b Rotating priority mode
c Special mask mode
d Polled mode
The OCWs can be written into the 8259A anytime
after initialization
8086 8088
8086 mode is similar to MCS-80 mode except that
only two Interrupt Acknowledge cycles are issued by
the processor and no CALL opcode is sent to the
processor The first interrupt acknowledge cycle is
similar to that of MCS-80 85 systems in that the
8259A uses it to internally freeze the state of the
interrupts for priority resolution and as a master it
issues the interrupt code on the cascade lines at the
end of the INTA pulse On this first cycle it does not
issue any data to the processor and leaves its data
bus buffers disabled On the second interrupt ac-
knowledge cycle in 8086 mode the master (or slave
if so programmed) will send a byte of data to the
processor with the acknowledged interrupt code
INITIALIZATION COMMAND WORDS
(ICWS)
General
Whenever a command is issued with A0 ^e 0 and D4
e _{1 this is interpreted as Initialization Command}
Word 1 (ICW1) ICW1 starts the intiitalization se-
quence during which the following automatically oc-
cur
a The edge sense circuit is reset which means that
following initialization an interrupt request (IR) in-
put must make a low-to-high transistion to gener-
ate an interrupt
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