8259A Datasheet, PDF (21/24 Pages) Intel Corporation – PROGRAMMABLE INTERRUPT CONTROLLER

8259A
A C CHARACTERISTICS T_A ^e 0 C to 70 C V_CC ^e 5V g10%
TIMING REQUIREMENTS
Symbol
Parameter
8259A
8259A-2 _{Units Test Conditions}
Min Max Min Max
v TAHRL AO CS Setup to RD INTA
0
0
ns
u TRHAX AO CS Hold after RD INTA
0
0
ns
TRLRH RD Pulse Width
235
160
ns
TAHWL
TWHAX
TWLWH
v AO CS Setup to WR
u AO CS Hold after WR
WR Pulse Width
0
0
ns
0
0
ns
290
190
ns
u TDVWH Data Setup to WR
240
160
u TWHDX Data Hold after WR
0
0
TJLJH Interrupt Request Width (Low)
100
100
ns
ns
ns
See Note 1
TCVIAL Cascade Setup to Second or Third
v INTA (Slave Only)
55
40
ns
TRHRL End of RD to Next RD
End of INTA to Next INTA within
160
100
ns
an INTA Sequence Only
TWHWL End of WR to Next WR
190
100
ns
TCHCL
End of Command to Next Command
(Not Same Command Type)
500
150
ns
End of INTA Sequence to Next
INTA Sequence
500
300
Worst case timing for TCHCL in an actual microprocessor system is typically much greater than 500 ns (i e 8085A e
1 6 ms 8085A-2 e 1 ms 8086 e 1 ms 8086-2 e 625 ns)
NOTE
This is the low time required to clear the input latch in the edge triggered mode
TIMING RESPONSES
Symbol
Parameter
8259A
8259A-2 _Units
Min Max Min Max
Test Conditions
v TRLDV Data Valid from RD INTA
200
120
ns
C of Data Bus ^e
100 pF
TRHDZ
TJHIH
TIALCV
u Data Float after RD INTA
Interrupt Output Delay
v Cascade Valid from First INTA
(Master Only)
10 100 10 85 ns C of Data Bus
350
300 ns ^{Max Test C e 100 pF}
Min Test C ^e 15 pF
565
360 ns C_INT e 100 pF
v v TRLEL Enable Active from RD or INTA
125
100 ns
C_CASCADE ^e 100 pF
u u TRHEH Enable Inactive from RD or INTA
150
150 ns
TAHDV Data Valid from Stable Address
200
200 ns
TCVDV Cascade Valid to Valid Data
300
200 ns
21