8259A Datasheet, PDF (14/24 Pages) Intel Corporation – PROGRAMMABLE INTERRUPT CONTROLLER

8259A
Operation Control Word 1 (OCW1)
OCW1 sets and clears the mask bits in the interrupt
Mask Register (IMR) M₇ – M₀ represent the eight
mask bits M ^e 1 indicates the channel is masked
(inhibited) M ^e 0 indicates the channel is enabled
Operation Control Word 2 (OCW2)
R SL EOI These three bits control the Rotate and
End of Interrupt modes and combinations of the two
A chart of these combinations can be found on the
Operation Command Word Format
L₂ L₁ L₀ These bits determine the interrupt level
acted upon when the SL bit is active
Figure 8 Operation Command Word Format (Continued)
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