8259A Datasheet, PDF (19/24 Pages) Intel Corporation – PROGRAMMABLE INTERRUPT CONTROLLER

8259A
CASCADE MODE
The 8259A can be easily interconnected in a system
of one master with up to eight slaves to handle up to
64 priority levels
The master controls the slaves through the 3 line
cascade bus The cascade bus acts like chip selects
to the slaves during the INTA sequence
In a cascade configuration the slave interrupt out-
puts are connected to the master interrupt request
inputs When a slave request line is activated and
afterwards acknowledged the master will enable the
corresponding slave to release the device routine
address during bytes 2 and 3 of INTA (Byte 2 only
for 8086 8088)
The cascade bus lines are normally low and will con-
tain the slave address code from the trailing edge of
the first INTA pulse to the trailing edge of the third
pulse Each 8259A in the system must follow a sep-
arate initialization sequence and can be pro-
grammed to work in a different mode An EOI com-
mand must be issued twice once for the master and
once for the corresponding slave An address de-
coder is required to activate the Chip Select (CS)
input of each 8259A
The cascade lines of the Master 8259A are activat-
ed only for slave inputs non-slave inputs leave the
cascade line inactive (low)
Figure 11 Cascading the 8259A
231468 – 24
19