8259A Datasheet, PDF (8/24 Pages) Intel Corporation – PROGRAMMABLE INTERRUPT CONTROLLER

8259A
231468 – 7
Figure 4c 8259A Block Diagram
INTERRUPT SEQUENCE OUTPUTS
MCS-80 MCS-85
This sequence is timed by three INTA pulses During
the first INTA pulse the CALL opcode is enabled
onto the data bus
Content of First Interrupt Vector Byte
D7 D6 D5 D4 D3 D2 D1 D0
CALL CODE
11001101
231468 – 8
Figure 5 8259A Interface to
Standard System Bus
During the second INTA pulse the lower address of
the appropriate service routine is enabled onto the
data bus When Interval ^e 4 bits A₅ – A₇ are pro-
grammed while A₀ – A₄ are automatically inserted by
the 8259A When Interval ^e 8 only A₆ and A₇ are
programmed while A₀ – A₅ are automatically insert-
ed
8