8259A Datasheet, PDF (2/24 Pages) Intel Corporation – PROGRAMMABLE INTERRUPT CONTROLLER

8259A
Symbol
V_CC
GND
CS
WR
RD
D₇ – D₀
CAS₀ – CAS₂
SP EN
INT
IR₀ – IR₇
INTA
A₀
Pin No
28
14
1
2
3
4 – 11
12 13 15
16
17
18 – 25
26
27
Type
I
I
I
I
I
IO
IO
IO
O
I
I
I
Table 1 Pin Description
Name and Function
SUPPLY ^a5V Supply
GROUND
CHIP SELECT A low on this pin enables RD and WR communication
between the CPU and the 8259A INTA functions are independent of
CS
WRITE A low on this pin when CS is low enables the 8259A to accept
command words from the CPU
READ A low on this pin when CS is low enables the 8259A to release
status onto the data bus for the CPU
BIDIRECTIONAL DATA BUS Control status and interrupt-vector
information is transferred via this bus
CASCADE LINES The CAS lines form a private 8259A bus to control
a multiple 8259A structure These pins are outputs for a master 8259A
and inputs for a slave 8259A
SLAVE PROGRAM ENABLE BUFFER This is a dual function pin
When in the Buffered Mode it can be used as an output to control
buffer transceivers (EN) When not in the buffered mode it is used as
an input to designate a master (SP ^e 1) or slave (SP ^e 0)
INTERRUPT This pin goes high whenever a valid interrupt request is
asserted It is used to interrupt the CPU thus it is connected to the
CPU’s interrupt pin
INTERRUPT REQUESTS Asynchronous inputs An interrupt request
is executed by raising an IR input (low to high) and holding it high until
it is acknowledged (Edge Triggered Mode) or just by a high level on an
IR input (Level Triggered Mode)
INTERRUPT ACKNOWLEDGE This pin is used to enable 8259A
interrupt-vector data onto the data bus by a sequence of interrupt
acknowledge pulses issued by the CPU
AO ADDRESS LINE This pin acts in conjunction with the CS WR and
RD pins It is used by the 8259A to decipher various Command Words
the CPU writes and status the CPU wishes to read It is typically
connected to the CPU A0 address line (A1 for 8086 8088)
2