8259A Datasheet, PDF (10/24 Pages) Intel Corporation – PROGRAMMABLE INTERRUPT CONTROLLER

8259A
b The Interrupt Mask Register is cleared
c IR7 input is assigned priority 7
d The slave mode address is set to 7
e Special Mask Mode is cleared and Status Read is
set to IRR
f If IC4 ^e 0 then all functions selected in ICW4
are set to zero (Non-Buffered mode no Auto-
EOI MCS-80 85 system)
NOTE
Master Slave in ICW4 is only used in the buffered
mode
Initialization Command Words 1 and 2
(ICW1 ICW2)
A₅–A₁₅ Page starting address of service routines
In an MCS 80 85 system the 8 request levels will
generate CALLs to 8 locations equally spaced in
memory These can be programmed to be spaced at
intervals of 4 or 8 memory locations thus the 8 rou-
tines will occupy a page of 32 or 64 bytes respec-
tively
The address format is 2 bytes long (A₀ – A₁₅) When
the routine interval is 4 A₀ – A₄ are automatically in-
serted by the 8259A while A₅ – A₁₅ are programmed
externally When the routine interval is 8 A₀ – A₅ are
automatically inserted by the 8259A while A₆ – A₁₅
are programmed externally
The 8-byte interval will maintain compatibility with
current software while the 4-byte interval is best for
a compact jump table
In an 8086 system A₁₅ – A₁₁ are inserted in the five
most significant bits of the vectoring byte and the
8259A sets the three least significant bits according
to the interrupt level A₁₀ – A₅ are ignored and ADI
(Address interval) has no effect
LTIM If LTIM ^e 1 then the 8259A will operate in
the level interrupt mode Edge detect logic
on the interrupt inputs will be disabled
ADI CALL address interval ADI ^e 1 then inter-
val ^e 4 ADI ^e 0 then interval ^e 8
SNGL Single Means that this is the only 8259A in
the system If SNGL ^e 1 no ICW3 will be
issued
IC4 If this bit is set ICW4 has to be read If
ICW4 is not needed set IC4 ^e 0
Initialization Command Word 3 (ICW3)
This word is read only when there is more than one
8259A in the system and cascading is used in which
case SNGL ^e 0 It will load the 8-bit slave register
The functions of this register are
a In the master mode (either when SP ^e 1 or in
buffered mode when M S ^e 1 in ICW4) a ‘‘1’’ is
set for each slave in the system The master then
will release byte 1 of the call sequence (for MCS-
80 85 system) and will enable the corresponding
slave to release bytes 2 and 3 (for 8086 only byte
2) through the cascade lines
b In the slave mode (either when SP ^e 0 or if BUF
e _{1 and M S} e _{0 in ICW4) bits 2 – 0 identify the}
slave The slave compares its cascade input with
these bits and if they are equal bytes 2 and 3 of
the call sequence (or just byte 2 for 8086) are
released by it on the Data Bus
231468 – 9
Figure 6 Initialization Sequence
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