8259A Datasheet, PDF (15/24 Pages) Intel Corporation – PROGRAMMABLE INTERRUPT CONTROLLER

8259A
Operation Control Word 3 (OCW3)
ESMM Enable Special Mask Mode When this bit
is set to 1 it enables the SMM bit to set or reset the
Special Mask Mode When ESMM ^e 0 the SMM bit
becomes a ‘‘don’t care’’
SMM Special Mask Mode If ESMM ^e 1 and SMM
e _{1 the 8259A will enter Special Mask Mode If}
ESMM ^e 1 and SMM ^e 0 the 8259A will revert to
normal mask mode When ESMM ^e 0 SMM has no
effect
When a mode is used which may disturb the fully
nested structure the 8259A may no longer be able
to determine the last level acknowledged In this
case a Specific End of Interrupt must be issued
which includes as part of the command the IS level
to be reset A specific EOI can be issued with OCW2
(EOI ^e 1 SL ^e 1 R ^e 0 and L0 – L2 is the binary
level of the IS bit to be reset)
It should be noted that an IS bit that is masked by an
IMR bit will not be cleared by a non-specific EOI if
the 8259A is in the Special Mask Mode
Fully Nested Mode
This mode is entered after initialization unless anoth-
er mode is programmed The interrupt requests are
ordered in priority from 0 through 7 (0 highest)
When an interrupt is acknowledged the highest pri-
ority request is determined and its vector placed on
the bus Additionally a bit of the Interrupt Service
register (ISO-7) is set This bit remains set until the
microprocessor issues an End of Interrupt (EOI)
command immediately before returning from the
service routine or if AEOI (Automatic End of Inter-
rupt) bit is set until the trailing edge of the last INTA
While the IS bit is set all further interrupts of the
same or lower priority are inhibited while higher lev-
els will generate an interrupt (which will be acknowl-
edged only if the microprocessor internal Interupt
enable flip-flop has been re-enabled through soft-
ware)
After the initialization sequence IR0 has the highest
prioirity and IR7 the lowest Priorities can be
changed as will be explained in the rotating priority
mode
End of Interrupt (EOI)
The In Service (IS) bit can be reset either automati-
cally following the trailing edge of the last in se-
quence INTA pulse (when AEOI bit in ICW1 is set) or
by a command word that must be issued to the
8259A before returning from a service routine (EOI
command) An EOI command must be issued twice
if in the Cascade mode once for the master and
once for the corresponding slave
There are two forms of EOI command Specific and
Non-Specific When the 8259A is operated in modes
which perserve the fully nested structure it can de-
termine which IS bit to reset on EOI When a Non-
Specific EOI command is issued the 8259A will auto-
matically reset the highest IS bit of those that are
set since in the fully nested mode the highest IS
level was necessarily the last level acknowledged
and serviced A non-specific EOI can be issued with
OCW2 (EOI ^e 1 SL ^e 0 R ^e 0)
Automatic End of Interrupt (AEOI)
Mode
If AEOI ^e 1 in ICW4 then the 8259A will operate in
AEOI mode continuously until reprogrammed by
ICW4 in this mode the 8259A will automatically per-
form a non-specific EOI operation at the trailing
edge of the last interrupt acknowledge pulse (third
pulse in MCS-80 85 second in 8086) Note that
from a system standpoint this mode should be used
only when a nested multilevel interrupt structure is
not required within a single 8259A
The AEOI mode can only be used in a master 8259A
and not a slave 8259As with a copyright date of
1985 or later will operate in the AEOI mode as a
master or a slave
Automatic Rotation
(Equal Priority Devices)
In some applications there are a number of interrupt-
ing devices of equal priority In this mode a device
after being serviced receives the lowest priority so
a device requesting an interrupt will have to wait in
the worst case until each of 7 other devices are
serviced at most once For example if the priority
and ‘‘in service’’ status is
Before Rotate (IR4 the highest prioirity requiring
service)
‘‘IS’’ Status
231468 – 18
Priority Status
231468 – 19
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