8259A Datasheet, PDF (17/24 Pages) Intel Corporation – PROGRAMMABLE INTERRUPT CONTROLLER

8259A
NOTES
1 Master clear active only during ICW1
2 FREEZE is active during INTA and poll sequences only
3 Truth Table for a D-Latch
C D Q Operation
231468 – 22
1 Di Di
Follow
0 X Qn-1 Hold
Figure 9 Priority Cell Simplified Logic Diagram
The following registers can be read via OCW3 (IRR
and ISR or OCW1 IMR )
Interrupt Request Register (IRR) 8-bit register which
contains the levels requesting an interrupt to be ac-
knowledged The highest request level is reset from
the IRR when an interrupt is acknowledged (Not af-
fected by IMR )
There is no need to write an OCW3 before every
status read operation as long as the status read
corresponds with the previous one i e the 8259A
‘‘remembers’’ whether the IRR or ISR has been pre-
viously selected by the OCW3 This is not true when
poll is used
After initialization the 8259A is set to IRR
In-Service Register (ISR) 8-bit register which con-
tains the priority levels that are being serviced The
ISR is updated when an End of Interrupt Command
is issued
Interrupt Mask Register 8-bit register which con-
tains the interrupt request lines which are masked
For reading the IMR no OCW3 is needed The out-
put data bus will contain the IMR whenever RD is
active and A0 ^e 1 (OCW1)
Polling overrides status read when P ^e 1 RR ^e 1
in OCW3
The IRR can be read when prior to the RD pulse a
Read Register Command is issued with OCW3 (RR
e _{1 RIS} e _{0 )}
Edge and Level Triggered Modes
This mode is programmed using bit 3 in ICW1
The ISR can be read when prior to the RD pulse a
Read Register Command is issued with OCW3 (RR
e _{1 RIS} e ₁₎
If LTIM ^e ‘0’ an interrupt request will be recognized
by a low to high transition on an IR input The IR
input can remain high without generating another in-
terrupt
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