80C186EA Datasheet, PDF (8/50 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EA 80C188EA 80L186EA 80L188EA
80C187 Interface (80C186EA Only)
The 80C187 Numerics Coprocessor may be used to
extend the 80C186EA instruction set to include
floating point and advanced integer instructions
Connecting the 80C186EA RESOUT and TEST
BUSY pins to the 80C187 enables Numerics Mode
operation In Numerics Mode three of the four Mid-
Range Chip Select (MCS) pins become handshaking
pins for the interface The exchange of data and
control information proceeds through four dedicated
I O ports
If an 80C187 is not present the 80C186EA config-
ures itself for regular operation at reset
NOTE
The 80C187 is not specified for 3V operation and
therefore does not interface directly to the
80L186EA
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system the 80C186EA has a test
mode available which forces all output and input
output pins to be placed in the high-impedance
state ONCE stands for ‘‘ON Circuit Emulation’’ The
ONCE mode is selected by forcing the UCS and LCS
pins LOW (0) during a processor reset (these pins
are weakly held to a HIGH (1) level) while RESIN is
active
DIFFERENCES BETWEEN THE
80C186XL AND THE 80C186EA
The 80C186EA is intended as a direct functional up-
grade for 80C186XL designs In many cases it will
be possible to replace an existing 80C186XL with
little or no hardware redesign The following sections
describe differences in pinout operating modes and
AC and DC specifications to keep in mind
Pinout Compatibility
The 80C186EA requires a PDTMR pin to time the
processor’s exit from Powerdown Mode The original
pin arrangement for the 80C186XL in the PLCC
package did not have any spare leads to use for
PDTMR so the DT R pin was sacrificed The ar-
rangement of all the other leads in the 68-lead PLCC
is identical between the 80C186XL and the
80C186EA DT R may be synthesized by latching
the S1 status output Therefore upgrading a PLCC
80C186XL to PLCC 80C186EA is straightforward
The 80-lead QFP (EIAJ) pinouts are different be-
tween the 80C186XL and the 80C186EA In addition
to the PDTMR pin the 80C186EA has more power
and ground pins and the overall arrangement of pins
was shifted A new circuit board layout for the
80C186EA is required
Operating Modes
The 80C186XL has two operating modes Compati-
ble and Enhanced Compatible Mode is a pin-to-pin
replacement for the NMOS 80186 except for nu-
merics coprocessing In Enhanced Mode the proc-
essor has a Refresh Control Unit the Power-Save
feature and an interface to the 80C187 Numerics
Coprocessor The MCS0 MCS1 and MCS3 pins
change their functions to constitute handshaking
pins for the 80C187
The 80C186EA allows all non-80C187 users to use
all the MCS pins for chip-selects In regular opera-
tion all 80C186EA features (including those of the
Enhanced Mode 80C186) are present except for the
interface to the 80C187 Numerics Mode disables
the three chip-select pins and reconfigures them for
connection to the 80C187
TTL vs CMOS Inputs
The inputs of the 80C186EA are rated for CMOS
switching levels for improved noise immunity but the
80C186XL inputs are rated for TTL switching levels
In particular the 80C186EA requires a minimum V_IH
of 3 5V to recognize a logic one while the 80C186XL
requires a minimum V_IH of only 1 9V (assuming 5 0V
operation) The solution is to drive the 80C186EA
with true CMOS devices such as those from the HC
and AC logic families or to use pullup resistors
where the added current draw is not a problem
Timing Specifications
80C186EA timing relationships are expressed in a
simplified format over the 80C186XL The AC per-
formance of an 80C186EA at a specified frequency
will be very close to that of an 80C186XL at the
same frequency Check the timings applicable to
your design prior to replacing the 80C186XL
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