80C186EA Datasheet, PDF (26/50 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EA 80C188EA 80L186EA 80L188EA
AC SPECIFICATIONS (Continued)
AC Characteristics 80C186EA25 80C186EA20 80C186EA13
Symbol
Parameter
SYNCHRONOUS INPUTS
Min Max
25 MHz⁽¹²⁾
Min Max
20 MHz
Min Max
13 MHz
T_CHIS
TEST NMI INT3 0
8
T1 0IN ARDY
10
10
T_CHIH
TEST NMI INT3 0
3
3
3
T1 0IN ARDY
T_CLIS
AD15 0 (AD7 0) ARDY
10
10
10
SRDY DRQ1 0
T_CLIH
AD15 0 (AD7 0) ARDY
3
3
3
SRDY DRQ1 0
T_CLIS
HOLD PEREQ ERROR 10
10
10
(80C186EA Only)
T_CLIH
HOLD PEREQ ERROR 3
3
3
(80C186EA Only)
T_CLIS
RESIN (to CLKIN)
10
10
10
T_CLIH
RESIN (from CLKIN)
3
3
3
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measured at V_IH for high time V_IL for low time
3 Only required to guarantee I_CC Maximum limits are bounded by T_C T_CH and T_CL
4 Specified for a 50 pF load see Figure 13 for capacitive derating information
5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF
6 See Figure 14 for rise and fall times
7 T_CHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release
8 T_CHOV2 applies to RD and WR only after a HOLD release
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper operation
11 T_CHOVS applies to BHE (RFSH) and A19 16 only after a HOLD release
12 Operating conditions for 25 MHz are 0 C to a70 C V_CC e 5 0V g10%
Pin names in parentheses apply to the 80C188EA 80L188EA
Units
ns
ns
ns
ns
ns
ns
ns
ns
Notes
19
19
1 10
1 10
19
19
19
19
26
26