80C186EA Datasheet, PDF (12/50 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EA 80C188EA 80L186EA 80L188EA
Table 3 Pin Descriptions (Continued)
Pin
Name
A18 16
A19 S6–A16
(A19 – A8)
S2 0
ALE QS0
BHE
(RFSH)
RD QSMD
Pin
Type
O
O
O
O
O
Input
Type
Output
States
H(Z)
R(Z)
P(X)
H(Z)
R(Z)
P(1)
H(0)
R(0)
P(0)
H(Z)
R(Z)
P(X)
H(Z)
R(WH)
P(1)
Description
These pins provide multiplexed Address during the address
phase of the bus cycle Address bits 16 through 19 are
presented on these pins and can be latched using ALE
A18 16 are driven to a logic 0 during the data phase of the bus
cycle On the 8-bit bus versions A15 – A8 provide valid address
information for the entire bus cycle Also during the data
phase S6 is driven to a logic 0 to indicate a CPU-initiated bus
cycle or logic 1 to indicate a DMA-initiated bus cycle or a
refresh cycle
Bus cycle Status are encoded on these pins to provide bus
transaction information S2 0 are encoded as follows
S2 S1 S0
Bus Cycle Initiated
00
00
01
01
10
10
11
11
0 Interrupt Acknowledge
1 Read I O
0 Write I O
1 Processor HALT
0 Queue Instruction Fetch
1 Read Memory
0 Write Memory
1 Passive (no bus activity)
Address Latch Enable output is used to strobe address
information into a transparent type latch during the address
phase of the bus cycle In Queue Status Mode QS0 provides
queue status information along with QS1
Byte High Enable output to indicate that the bus cycle in
progress is transferring data over the upper half of the data
bus BHE and A0 have the following logical encoding
A0
BHE Encoding (For 80C186EA 80L186EA Only)
0
0 Word Transfer
0
1 Even Byte Transfer
1
0 Odd Byte Transfer
1
1 Refresh Operation
On the 80C188EA 80L188EA RFSH is asserted low to
indicate a Refresh bus cycle
ReaD output signals that the accessed memory or I O device
must drive data information onto the data bus Upon reset this
pin has an alternate function As QSMD it enables Queue
Status Mode when grounded In Queue Status Mode the
ALE QS0 and WR QS1 pins provide the following information
about processor instruction queue interaction
QS1 QS0
Queue Operation
0
0 No Queue Operation
0
1 First Opcode Byte Fetched from the Queue
1
1 Subsequent Byte Fetched from the Queue
1
0 Empty the Queue
NOTE
Pin names in parentheses apply to the 80C188EA and 80L188EA
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