80C186EA Datasheet, PDF (27/50 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EA 80C188EA 80L186EA 80L188EA
AC SPECIFICATIONS
AC Characteristics 80L186EA13 80L186EA8
Symbol
Parameter
Min
Max
INPUT CLOCK
13 MHz
T_F
CLKIN Frequency
T_C
CLKIN Period
T_CH
CLKIN High Time
T_CL
CLKIN Low Time
T_CR
CLKIN Rise Time
T_CF
CLKIN Fall Time
OUTPUT CLOCK
0
26
38 5
%
12
%
12
%
1
8
1
8
T_CD
CLKIN to CLKOUT Delay
T
CLKOUT Period
T_PH
CLKOUT High Time
T_PL
CLKOUT Low Time
T_PR
CLKOUT Rise Time
T_PF
CLKOUT Fall Time
OUTPUT DELAYS
0
(T 2) ^b 5
(T 2) ^b 5
1
1
45
2 T_C
12
12
T_CHOV1
T_CHOV2
ALE LOCK
MCS3 0 LCS UCS
PCS6 0 RD WR
3
27
3
32
T_CHOV3 S2 0 (DEN) DT R
BHE (RFSH) A19 16
3
30
T_CLOV1
LOCK RESOUT HLDA
T0OUT T1OUT
3
27
T_CLOV2
RD WR MCS3 0 LCS
UCS PCS6 0 INTA1 0
3
32
T_CLOV3 BHE (RFSH) DEN A19 16
3
30
T_CLOV4 AD15 0 (A15 8 AD7 0)
3
34
T_CLOV5 S2 0
3
38
T_CHOF
RD WR BHE (RFSH)
DT R LOCK
S2 0 A19 16
0
27
T_CLOF
DEN AD15 0
(A15 8 AD7 0)
0
27
Min
Max
8 MHz
0
16
62 5
%
12
%
12
%
1
8
1
8
0
(T 2) ^b 5
(T 2) ^b 5
1
1
95
2 T_C
12
12
3
27
3
32
3
30
3
27
3
35
3
30
3
35
3
40
0
27
0
27
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measured at V_IH for high time V_IL for low time
3 Only required to guarantee I_CC Maximum limits are bounded by T_C T_CH and T_CL
4 Specified for a 50 pF load see Figure 13 for capacitive derating information
5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF
6 See Figure 14 for rise and fall times
7 T_CHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release
8 T_CHOV2 applies to RD and WR only after a HOLD release
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper operation
11 T_CHOVS applies to BHE (RFSH) and A19 16 only after a HOLD release
12 Pin names in parentheses apply to the 80C188EA 80L188EA
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
12
12
13
13
14
1
1
1
15
15
1467
14
68
1
146
146
146
146
146
1
1
27
27