80C186EA Datasheet, PDF (24/50 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EA 80C188EA 80L186EA 80L188EA
I_CC VERSUS FREQUENCY AND VOLTAGE
The current (I_CC) consumption of the processor is
essentially composed of two components I_PD and
I_CCS
I_PD is the quiescent current that represents internal
device leakage and is measured with all inputs or
floating outputs at GND or V_CC (no clock applied to
the device) I_PD is equal to the Powerdown current
and is typically less than 50 mA
I_CCS is the switching current used to charge and
discharge parasitic device capacitance when chang-
ing logic levels Since I_CCS is typically much greater
than I_PD I_PD can often be ignored when calculating
I_CC
I_CCS is related to the voltage and frequency at which
the device is operating It is given by the formula
Where
Power ^e V ^c I ^e V^{2 c} C_DEV ^c f
I ^e I_CC ^e I_CCS ^e V ^c C_DEV ^c f
V ^e Device operating voltage (V_CC)
C_DEV ^e Device capacitance
f ^e Device operating frequency
I_CCS ^e I_CC ^e Device current
Measuring C_DEV on a device like the 80C186EA
would be difficult Instead C_DEV is calculated using
the above formula by measuring I_CC at a known V_CC
and frequency (see Table 11) Using this C_DEV val-
ue I_CC can be calculated at any voltage and fre-
quency within the specified operating range
EXAMPLE Calculate the typical I_CC when operating
at 20 MHz 4 8V
I_CC ^e I_CCS ^e 4 8 ^c 0 515 ^c 20 49 mA
PDTMR PIN DELAY CALCULATION
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown A delay is required
only when using the on-chip oscillator to allow the
crystal or resonator circuit time to stabilize
NOTE
The PDTMR pin function does not apply when
RESIN is asserted (i e a device reset during Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabi-
lized)
To calculate the value of capacitor required to pro-
vide a desired delay use the equation
440 ^c t ^e C_PD (5V 25 C)
Where t ^e desired delay in seconds
C_PD ^e capacitive load on PDTMR in mi-
crofarads
EXAMPLE To get a delay of 300 ms a capacitor
value of C_PD ^e 440 ^c (300 ^c 10^b6) ^e 0 132 mF is
required Round up to standard (available) capaci-
tive values
NOTE
The above equation applies to delay times greater
than 10 ms and will compute the TYPICAL capaci-
tance needed to achieve the desired delay A delay
variance of ^a50% or ^b25% can occur due to
temperature voltage and device process ex-
tremes In general higher V_CC and or lower tem-
perature will decrease delay time while lower V_CC
and or higher temperature will increase delay time
Parameter
Table 11 C_DEV Values
Typ
Max
Units
Notes
C_DEV (Device in Reset)
0 515
0 905
mA V MHz
12
C_DEV (Device in Idle)
0 391 0 635 mA V MHz
12
1 Max C_DEV is calculated at b40 C all floating outputs driven to V_CC or GND and all
outputs loaded to 50 pF (including CLKOUT and OSCOUT)
2 Typical C_DEV is calculated at 25 C with all outputs loaded to 50 pF except CLKOUT and
OSCOUT which are not loaded
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