80C186EA Datasheet, PDF (22/50 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EA 80C188EA 80L186EA 80L188EA
DC SPECIFICATIONS (80C186EA 80C188EA)
Symbol
Parameter
Min
Max Units
Conditions
V_CC
V_IL
V_IH
V_OL
V_OH
V_HYR
I_IL1
Supply Voltage
45
55
V
Input Low Voltage for All Pins
Input High Voltage for All Pins
Output Low Voltage
Output High Voltage
Input Hysterisis on RESIN
b_{0 5}
0 3 V_CC
V
0 7 V_CC V_CC ^a 0 5 V
0 45
V I_OL ^e 3 mA (min)
V_CC ^b 0 5
V I_OH ^{e b}2 mA (min)
0 30
V
Input Leakage Current (except
RD QSMD UCS LCS MCS0 PEREQ
MCS1 ERROR LOCK and TEST BUSY)
g10
mA 0V ^s V_IN ^s V_CC
I_IL2
Input Leakage Current
b₂₇₅
(RD QSMD UCS LCS MCS0 PEREQ
MCS1 ERROR LOCK and TEST BUSY
mA V_IN ^e 0 7 V_CC
(Note 1)
I_OL
Output Leakage Current
g10
mA
0 45 ^s V_OUT ^s V_CC
(Note 2)
I_CC
Supply Current Cold (RESET)
80C186EA25 80C188EA25
80C186EA20 80C188EA20
80C186EA13 80C188EA13
105
mA (Notes 3 5)
90
mA
65
mA
I_ID
Supply Current In Idle Mode
80C186EA25 80C188EA25
80C186EA20 80C188EA20
80C186EA13 80C188EA13
90
mA (Note 5)
70
mA
46
mA
I_PD
Supply Current In Powerdown Mode
80C186EA25 80C188EA25
80C186EA20 80C188EA20
80C186EA13 80C188EA13
100
mA (Note 5)
100
mA
100
mA
C_OUT
C_IN
Output Pin Capacitance
Input Pin Capacitance
0
15
pF T_F ^e 1 MHz (Note 4)
0
15
pF T_F ^e 1 MHz
NOTES
1 RD QSMD UCS LCS MCS0 PEREQ MCS1 ERROR LOCK and TEST BUSY have internal pullups that are only acti-
vated during RESET Loading these pins above I_OL e b275 mA will cause the processor to enter alternate modes of
operation
2 Output pins are floated using HOLD or ONCE Mode
3 Measured at worst case temperature and V_CC with all outputs loaded as specified in the AC Test Conditions and with the
device in RESET (RESIN held low) RESET is worst case for I_CC
4 Output capacitance is the capacitive load of a floating output pin
5 Operating conditions for 25 MHz are 0 C to a70 C V_CC e 5 0V g10%
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