80C186EA Datasheet, PDF (29/50 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186EA 80C188EA 80L186EA 80L188EA
AC SPECIFICATIONS (Continued)
Relative Timings (80C186EA25 20 13 80L186EA13 8)
Symbol
Parameter
RELATIVE TIMINGS
T_LHLL
T_AVLL
T_PLLL
T_LLAX
T_LLWL
T_LLRL
T_RHLH
T_WHLH
T_AFRL
T_RLRH
T_WLWH
T_RHAV
T_WHDX
T_WHDEX
T_WHPH
T_RHPH
T_PHPL
T_DXDL
T_OVRH
T_RHOX
ALE Rising to ALE Falling
Address Valid to ALE Falling
Chip Selects Valid to ALE Falling
Address Hold from ALE Falling
ALE Falling to WR Falling
ALE Falling to RD Falling
RD Rising to ALE Rising
WR Rising to ALE Rising
Address Float to RD Falling
RD Falling to RD Rising
WR Falling to WR Rising
RD Rising to Address Active
Output Data Hold after WR Rising
WR Rising to DEN Rising
WR Rising to Chip Select Rising
RD Rising to Chip Select Rising
CS Inactive to CS Active
DEN Inactive to DT R Low
ONCE (UCS LCS) Active to RESIN Rising
ONCE (UCS LCS) to RESIN Rising
Min
T ^b 15
T ^b 10
T ^b 10
T ^b 10
T ^b 15
T ^b 15
T ^b 10
T ^b 10
0
(2 T) ^b 5
(2 T) ^b 5
T ^b 15
T ^b 15
T ^b 10
T ^b 10
T ^b 10
T ^b 10
0
T
T
NOTES
1 Assumes equal loading on both pins
2 Can be extended using wait states
3 Not tested
4 Not applicable to latched A2 1 These signals change only on falling T₁
5 For write cycle followed by read cycle
6 Operating conditions for 25 MHz are 0 C to a70 C V_CC e 5 0V g10%
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1
1
1
2
2
1
14
14
1
5
3
3
29
29