80960CF-30 Datasheet, PDF (8/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR

SPECIAL ENVIRONMENT 80960CF-30 -25 -16
3 0 PACKAGE INFORMATION
3 1 Package Introduction
This section describes the pins pinouts and thermal
characteristics for the 80960CF in the 168-pin Ce-
ramic Pin Grid Array (PGA) package For complete
package specifications and information see the Intel
Packaging Outlines and Dimensions Guide (Order
No 231369)
3 2 Pin Descriptions
The 80960CF pins are described in this section Ta-
ble 1 presents the legend for interpreting the pin de-
scriptions in the following tables
Pins associated with the 32-bit demultiplexed proc-
essor bus are described in Table 2 Pins associated
with basic processor configuration and control are
described in Table 3 Pins associated with the
80960CF DMA Controller and Interrupt Unit are de-
scribed in Table 4
Figure 3 provides an example pin description table
entry ‘‘I O’’ signifies that data pins are input-output
‘‘S’’ indicates pins are synchronous to PCLK2 1
‘‘H(Z)’’ indicates that these pins float while the proc-
essor bus is in a Hold Acknowledge state ‘‘R(Z)’’
indicates that the pins also float while RESET is low
All pins float while the processor is in the ONCE
mode
Table 1 Pin Description Nomenclature
Symbol
Description
I
Input only pin
O
Output only pin
I O Pin can be either an input or output
-
Pins ‘‘must be’’ connected as
described
S( ) Synchronous Inputs must meet setup
and hold times relative to PCLK2 1 for
proper operation All outputs are
synchronous to PCLK2 1
S(E) Edge sensitive input
S(L) Level sensitive input
A( ) Asynchronous Inputs may be
asynchronous to PCLK2 1
A(E) Edge sensitive input
A(L) Level sensitive input
H( ) While the processor’s bus is in the
Hold Acknowledge or Bus Backoff
state the pin
H(1)
H(0)
H(Z)
is driven to V_CC
is driven to V_SS
floats
H(Q) continues to be a valid output
R( ) While the processor’s RESET pin is
low the pin
R(1)
R(0)
R(Z)
is driven to V_CC
is driven to V_SS
floats
R(Q) continues to be a valid output
Name Type
Description
D31 0
IO
S(L)
H(Z)
R(Z)
DATA BUS carries 32- 16- or 8-bit data quantities depending on bus width configuration
The least significant bit of the data is carried on D0 and the most significant on D31 When
the bus is configured for 8-bit data the lower 8 data lines D7 0 are used For 16-bit bus
widths D15 0 are used For 32-bit bus widths the full data bus is used
Figure 3 Example Pin Description Entry
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