80960CF-30 Datasheet, PDF (35/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR

SPECIAL ENVIRONMENT 80960CF-30 -25 -16
5 0 RESET BACKOFF AND HOLD
ACKNOWLEDGE
The following table lists the condition of each proc-
essor output pin while RESET is asserted (low)
Table 10 Reset Conditions
Pins
State During Reset
(HOLDA inactive)¹
A31 A2
Floating
D31 D0
Floating
BE3 0
Driven high (Inactive)
WR
Driven low (Read)
ADS
Driven high (Inactive)
WAIT
Driven high (Inactive)
BLAST
Driven low (Active)
DT R
Driven low (Receive)
DEN
Driven high (Inactive)
LOCK
Driven high (Inactive)
BREQ
Driven low (Inactive)
DC
Floating
DMA
Floating
SUP
Floating
FAIL
Driven low (Active)
DACK3
Driven high (Inactive)
DACK2
Driven high (Inactive)
DACK1
Driven high (Inactive)
DACK0
Driven high (Inactive)
EOP TC3
Floating (set to input mode)
EOP TC2
Floating (set to input mode)
EOP TC1
Floating (set to input mode)
EOP TC0
Floating (set to input mode)
NOTE
(1) With regard to bus output pin state only the Hold Ac-
knowledge state takes precedence over the reset state Al-
though asserting the RESET pin will internally reset the
processor the processor’s bus output pins will not enter
the reset state if it has granted Hold Acknowledge to a pre-
vious HOLD request (HOLDA is active) Furthermore the
processor will grant new HOLD requests and enter the
Hold Acknowledge state even while in reset
For example if HOLDA is not active and the processor is
in the reset state then HOLD is asserted the processor’s
bus pins will enter the Hold Acknowledge state and
HOLDA will be granted The processor will not be able to
perform memory accesses until the HOLD request is re-
moved even if the RESET pin is brought high This opera-
tion is provided to simplify boot-up synchronization among
multiple processors sharing the same bus
The following table lists the condition of each proc-
essor output pin while HOLDA is asserted (low)
Table 11 Hold Acknowledge
and Backoff Conditions
Pins
State During HOLDA
A31 A2
Floating
D31 D0
Floating
BE3 0
Floating
WR
Floating
ADS
Floating
WAIT
Floating
BLAST
Floating
DT R
Floating
DEN
Floating
LOCK
Floating
BREQ
Driven (high or low)
DC
Floating
DMA
Floating
SUP
Floating
FAIL
Driven high (Inactive)
DACK3
Driven high (Inactive)
DACK2
Driven high (Inactive)
DACK1
Driven high (Inactive)
DACK0
Driven high (Inactive)
EOP TC3
Driven if output
EOP TC2
Driven if output
EOP TC1
Driven if output
EOP TC0
Driven if output
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