80960CF-30 Datasheet, PDF (25/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR

SPECIAL ENVIRONMENT 80960CF-30 -25 -16
AC Characteristics 80960CF-30
(80960CF-30 only under the conditions described in Section 4 2 Operating Conditions and Section 4 5 1
AC Test Conditions ) See notes which follow this table (Continued)
Symbol
Parameter
Min
Max
Units Notes
RELATIVE OUTPUT TIMINGS^{(9 7)}
T_AVSH1
T_AVSH2
A31 2 Valid to ADS Rising
BE3 0 W R SUP D C
DMA DACK3 0 Valid to ADS Rising
Tb4
Tb6
Ta4
ns
Ta6
ns
T_AVEL1
T_AVEL2
A31 2 Valid to DEN Falling
BE3 0 W R SUP INST
DMA DACK3 0 Valid to DEN Falling
Tb4
Tb6
Ta4
ns
Ta6
ns
T_NLQV
WAIT Falling to Output Data Valid
g6
ns
T_DVNH Output Data Valid to WAIT Rising
N Tb6
N Ta6
ns
(4)
T_NLNH
WAIT Falling to WAIT Rising
N Tg4
ns
(4)
T_NHQX
Output Data Hold after WAIT Rising
(N a 1) T b 6 (N a 1) T a 6
ns
(5)
T_EHTV
DT R Hold after DEN High
T 2b6
%
ns
(6)
T_TVEL
DT R Valid to DEN Falling
T 2b4
T 2a4
ns
(7)
RELATIVE INPUT TIMINGS⁽⁷⁾
T_IS5
RESET Input Setup (2x Clock Mode)
T_IH5
RESET Input Hold (2x Clock Mode)
T_IS6
DREQ3 0 Input Setup
T_IH6
DREQ3 0 Input Hold
T_IS7
XINT7 0 NMI Input Setup
T_IH7
XINT7 0 NMI Input Hold
T_IS8
RESET Input Setup (1x Clock Mode)
T_IH8
RESET Input Hold (1x Clock Mode)
6
5
12
7
7
3
3
T 4a1
ns
(14)
ns
(14)
ns
(8)
ns
(8)
ns
(8)
ns
(8)
ns
(15)
ns
(15)
NOTES
1 See Section 4 5 2 AC Timing Waveforms for waveforms and definitions
2 See Figure 22 for capacitive derating information for output delays and hold times
3 See Figure 23 for capacitive derating information for rise and fall times
4 Where N is the number of N_RAD N_RDD N_WAD or N_WDD wait states that are programmed in the Bus Controller Region
Table When there are no wait states in an access WAIT never goes active
5 N e Number of wait states inserted with READY
6 Output Data and or DT R may be driven indefinitely following a cycle if there is no subsequent bus activity
7 See Notes 1 2 and 3
8 Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in order
to be recognized and for proper operation However to guarantee recognition of the input at a particular edge of PCLK2 1
the setup times shown must be met Asynchronous inputs must be active for at least two consecutive PCLK2 1 rising
edges to be seen by the processor
9 These specifications are guaranteed by the processor
10 These specifications must be met by the system for proper operation of the processor
11 This timing is dependent upon the loading of PCLK2 1 Use the derating curves of Section 4 5 3 to adjust the timing for
PCLK2 1 loading
12 In the 1-x input clock mode the maximum input clock period is limited to 125 ns while the processor is operating When
the processor is in reset the input clock may stop even in 1-x mode
13 When in the 1-x input clock mode these specifications assume a stable input clock with a period variation of less than
g0 1% between adjacent cycles
14 In 2x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation
However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup
and hold times to the falling edge of the CLKIN (See Figure 28a )
15 In 1x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation
However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must be deasserted
while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN (See Figure 28b )
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