80960CF-30 Datasheet, PDF (11/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR

SPECIAL ENVIRONMENT 80960CF-30 -25 -16
Name
HOLDA
BREQ
DC
DMA
SUP
Table 2 80960CF Pin Description External Bus Signals (Continued)
Type
Description
O
S
H(1)
R(Q)
HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has
relinquished control of the external bus When HOLDA is asserted the external
address bus data bus and bus control signals are floated HOLD BOFF HOLDA
and BREQ are used together to arbitrate access to the processor’s external bus
by external bus agents Since the processor grants HOLD requests and enters the
Hold Acknowledge state even while RESET is asserted HOLDA pin state is
independent of the RESET pin
O
S
H(Q)
R(0)
BUS REQUEST is asserted when the bus controller has a request pending BREQ
can be used by external bus arbitration logic in conjunction with HOLD and
HOLDA to determine when to return mastership of the external bus to the
processor
O
S
H(Z)
R(Z)
DATA OR CODE is asserted for a data request and deasserted for instruction
requests D C has the same timing as W R
O
S
H(Z)
R(Z)
DMA ACCESS indicates whether the bus request was initiated by the DMA
controller DMA is asserted for any DMA request DMA is deasserted for all other
requests
O
S
H(Z)
R(Z)
SUPERVISOR ACCESS indicates whether the bus request is issued while in
supervisor mode SUP is asserted when the request has supervisor privileges and
is deasserted otherwise SUP can be used to isolate supervisor code and data
structures from non-supervisor requests
Name
RESET
FAIL
Type
I
A(L)
H(Z)
R(Z)
N(Z)
O
S
H(Q)
R(0)
Table 3 80960CF Pin Description Processor Control Signals
Description
RESET causes the chip to reset When RESET is asserted all external signals return
to the reset state When RESET is deasserted initialization begins When the 2-x clock
mode is selected RESET must remain asserted for 16 PCLK2 1 cycles before being
deasserted in order to guarantee correct processor initialization When the 1-x clock
mode is selected RESET must remain asserted for 10 000 PCLK2 1 cycles before
being deasserted in order to guarantee correct initialization The CLKMODE pin
selects 1-x or 2-x input clock division of the CLKIN pin
The processor’s Hold Acknowledge bus state functions while the chip is reset If the
processor’s bus is in the Hold Acknowledge state when RESET is asserted the
processor will internally reset but maintains the Hold Acknowledge state on external
pins until the Hold request is removed If a hold request is made while the processor is
in the reset state the processor bus grants HOLDA and enters the Hold Acknowledge
state
FAIL indicates failure of the processor’s self-test performed at initialization When
RESET is deasserted and the processor begins initialization the FAIL pin is asserted
An internal self-test is performed as part of the initialization process If this self-test
passes the FAIL pin is deasserted otherwise it remains asserted The FAIL pin is
reasserted while the processor performs an external bus self-confidence test If this
self-test passes the processor deasserts the FAIL pin and branches to the user’s
initialization routine otherwise the FAIL pin remains asserted Internal self-test and the
use of the FAIL pin can be disabled with the STEST pin
11