80960CF-30 Datasheet, PDF (14/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR

SPECIAL ENVIRONMENT 80960CF-30 -25 -16
3 3 80960CF Pinout
3 3 1 80960CF PGA PINOUT
Tables 5 and 6 list the 80960CF pin names with
package location Figure 4-a depicts the complete
80960CF pinout as viewed from the top side of the
component (i e pins facing down) Figure 4b shows
the complete 80960CF pinout as viewed from the
pin-side of the package (i e pins facing up) See
Section 4 0 Electrical Specifications for specifica-
tions and recommended connections
Address Bus
Name Location
A31
S15
A30
Q13
A29
R14
A28
Q14
A27
S16
A26
R15
A25
S17
A24
Q15
A23
R16
A22
R17
A21
Q16
A20
P15
A19
P16
A18
Q17
A17
P17
A16
N16
A15
N17
A14
M17
A13
L16
A12
L17
A11
K17
A10
J17
A9
H17
A8
G17
A7
G16
A6
F17
A5
E17
A4
E16
A3
D17
A2
D16
Table 5 PGA Pin Name with Package Location (Signal Order)
Data Bus
Bus Control
Processor Control
Name Location Name Location Name Location
D31
R03 BE3
S05 RESET
A16
D30
Q05 BE2
S06
D29
S02 BE1
S07 FAIL
A02
D28
Q04 BE0
R09
D27
R02
STEST
B02
D26
Q03 W R
S10
D25
S01
ONCE
C03
D24
R01 ADS
R06
D23
Q02
CKLIN
C13
D22
P03 READY
S03 CLKMODE C14
D21
Q01 BTERM R04 PCLK1
B14
D20
P02
PCLK2
B13
D19
P01 WAIT
S12
D18
N02 BLAST
S08
V_SS
D17
N01
Location
D16
M01 DT R
S11 C07 C08 C09
D15
L01 DEN
S09
C10 C11 C12
F15 G03 G15
D14
L02
H03 H15 J03
D13
K01 LOCK
S14
J15 K03 K15
L03 L15 M03
D12
J01
M15 Q07 Q08
D11
H01 HOLD
R05 ^{Q09 Q10 Q11}
D10
H02 HOLDA
S04
V_CC
D9
G01 BREQ
R13
Location
D8
F01
B07 B09
D7
E01 D C
S13
B11 B12 C06
E15 F03 F16
D6
F02 DMA
R12 G02 H16 J02
D5
D01 SUP
Q12
J16 K02 K16 M02
M16 N03 N15
D4
E02
Q06 R07 R08
R10 R11
V_CCPLL
B10
D3
C01 BOFF
B01
No Connect
D2
D02
Location
D1
C02
A01 A03 A04 A05
B03 B04 C04 C05
D03
D0
E03
IO
Name Location
DREQ3
A07
DREQ2
B06
DREQ1
A06
DREQ0
B05
DACK3
A10
DACK2
A09
DACK1
A08
DACK0
B08
EOP TC0 A11
EOP TC1 A12
EOP TC2 A13
EOP TC3 A14
XINT7
C17
XINT6
C16
XINT5
B17
XINT4
C15
XINT3
B16
XINT2
A17
XINT1
A15
XINT0
B15
NMI
D15
14