80960CF-30 Datasheet, PDF (29/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR

SPECIAL ENVIRONMENT 80960CF-30 -25 -16
AC Characteristics 80960CF-16
(80960CF-16 only under the conditions described in Section 4 2 Operating Conditions and Section 4 5 1
AC Test Conditions ) (Continued)
Symbol
T_AVSH1
T_AVSH2
T_AVEL1
T_AVEL2
T_NLQV
T_DVNH
T_NLNH
T_NHQX
T_EHTV
T_TVEL
T_IS5
T_IH5
T_IS6
T_IH6
T_IS7
T_IH7
T_IS8
T_IH8
Parameter
Min
Max
RELATIVE OUTPUT TIMINGS^{(9 7)}
A31 2 Valid to ADS Rising
T^b4
T^a4
BE3 0 W R SUP D C
DMA DACK3 0 Valid to ADS Rising
T^b6
T^a6
A31 2 Valid to DEN Falling
T^b6
T^a6
BE3 0 W R SUP INST
DMA DACK3 0 Valid to DEN Falling
T^b6
T^a6
WAIT Falling to Output Data Valid
g6
Output Data Valid to WAIT Rising
N T^b6
N T^a6
WAIT Falling to WAIT Rising
N Tg4
Output Data Hold after WAIT Rising (N ^a 1) T ^b 6 (N ^a 1) T ^a 6
DT R Hold after DEN High
T 2^b6
%
DT R Valid to DEN Falling
T 2^b4
T 2^a4
RELATIVE INPUT TIMINGS⁽⁷⁾
RESET Input Setup (2x Clock Mode)
10
RESET Input Hold (2x Clock Mode)
9
DREQ3 0 Input Setup
16
DREQ3 0 Input Hold
11
XINT7 0 NMI Input Setup
9
XINT7 0 NMI Input Hold
5
RESET Input Setup (1x Clock Mode)
3
RESET Input Hold (1x Clock Mode)
T 4^a1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(4)
(4)
(5)
(6)
(7)
(14)
(14)
(8)
(8)
(8)
(8)
(15)
(15)
NOTES
(1) See Section 4 5 2 AC Timing Waveforms for waveforms and definitions
(2) See Figure 22 for capacitive derating information for output delays and hold times
(3) See Figure 23 for capacitive derating information for rise and fall times
(4) Where N is the number of N_RAD N_RDD N_WAD or N_WDD wait states that are programmed in the Bus Controller Region
Table When there are no wait states in an access WAIT never goes active
(5) N e Number of wait state inserted with READY
(6) Output Data and or DT R may be driven indefinitely following a cycle if there is no subsequent bus activity
(7) See Notes 1 2 and 3
(8) Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in
order to be recognized and for proper operation However to guarantee recognition of the input at a particular edge of
PCLK2 1 the setup times shown must be met Asynchronous inputs must be active for at least two consecutive PCLK2 1
rising edges to be seen by the processor
(9) These specifications are guaranteed by the processor
(10) These specifications must be met by the system for proper operation of the processor
(11) This timing is dependent upon the loading of PCLK2 1 Use the derating curves of Figure 22 to adjust the timing for
PCLK2 1 loading
(12) In the 1-x input clock mode the maximum input clock period is limited to 125 ns while the processor is operating When
the processor is in reset the input clock may stop even in 1-x mode
(13) When in the 1-x input clock mode these specifications assume a stable input clock with a period variation of less than
g0 1% between adjacent cycles
(14) In 2x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation
However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup and
hold times to the falling edge of the CLKIN (See Figure 28a )
(15) In 1x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation
However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must be deasserted
while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN (See Figure 28b )
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