80960CF-30 Datasheet, PDF (13/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR

SPECIAL ENVIRONMENT 80960CF-30 -25 -16
Table 4 80960CF Pin Description DMA and Interrupt Unit Control Signals
Name
Type
Description
DREQ3
DREQ2
DREQ1
DREQ0
I
A(L)
H(Z)
R(Z)
DMA REQUEST causes a DMA transfer to be requested Each of the four signals
request a transfer on a single channel DREQ0 requests channel 0 DREQ1 requests
channel 1 etc When two or more channels are requested simultaneously the
channel with the highest priority is serviced first Channel priority mode is
programmable
DACK3
DACK2
DACK1
DACK0
O DMA ACKNOWLEDGE indicates that a DMA transfer is being executed Each of the
S four signals acknowledge a transfer for a single channel DACK0 acknowledges
H(1) ^{channel 0 DACK1 acknowledges channel 1 etc DACK3 0 are asserted when the}
R(1) ^{requesting device of a DMA is accessed}
EOP3 TC3
EOP2 TC2
EOP1 TC1
EOP0 TC0
IO
A(L)
H(Z Q)
R(Z)
END OF PROCESS TERMINAL COUNT can be programmed as either an input
(EOP3 0) or as an output (TC3 0) but not both Each pin is individually
programmable When programmed as an input EOPx causes the termination of a
current DMA transfer for the channel corresponding to the EOPx pin EOP0
corresponds to channel 0 EOP1 corresponds to channel 1 etc When a channel is
configured for source and destination chaining the EOP pin for that channel causes
termination of only the current buffer transferred and causes the next buffer to be
transferred EOP3 0 are asynchronous inputs
When programmed as an output the channel’s TCx pin indicates that the channel
byte count has reached 0 and a DMA has terminated TCx is driven with the same
timing as DACKx during the last DMA transfer for a buffer If the last bus request is
executed as multiple bus accesses TCx remains asserted for the entire bus request
XINT7
XINT6
XINT5
XINT4
XINT3
XINT2
XINT1
XINT0
I
A(E L)
H(Z)
R(Z)
EXTERNAL INTERRUPT PINS cause interrupts to be requested These pins can be
configured in three modes
In Dedicated Mode each pin is a dedicated external interrupt source Dedicated
inputs can be individually programmed to be level (low) or edge (falling) activated
In Expanded Mode the 8 pins act together as an 8-bit vectored interrupt source The
interrupt pins in this mode are level activated Since the interrupt pins are active low
the vector number requested is the one’s complement of the positive logic value
place on the port This eliminates glue logic to interface to combinational priority
encoders which output negative logic
In Mixed Mode XINT7 5 are dedicated sources and XINT4 0 act as the 5 most
significant bits of an expanded mode vector The least significant bits are set to 010
internally
NMI
I NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur
A(E) NMI is the highest priority interrupt recognized NMI is an edge (falling) activated
H(Z) ^source
R(Z)
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