300 Datasheet, PDF (72/95 Pages) DB Lectro Inc – SCREW TYPE SERIES

Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
THERMTRIP#
TMS
TRDY#
TRST#
VCC
VCCA
VCCIOPLL
VCC_SENSE
VCC_MB_
REGULATION
VID[5:0]
VSS
VSSA
VSS_SENSE
Output
In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a temperature
approximately 20 °C above the maximum T_C. Assertion of
THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond where permanent silicon
damage may occur. Upon assertion of THERMTRIP#, the processor
will shut off its internal clocks (thus, halting program execution) in
an attempt to reduce the processor junction temperature. To protect
the processor, its core voltage (V_CC) must be removed following the
assertion of THERMTRIP#. Driving of the THERMTRIP# signal is
enabled within 10 μs of the assertion of PWRGOOD and is disabled
on de-assertion of PWRGOOD. Once activated, THERMTRIP#
remains latched until PWRGOOD is de-asserted. While the de-
assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the
processor’s junction temperature remains at or above the trip level,
THERMTRIP# will again be asserted within 10 μs of the assertion of
PWRGOOD.
Input
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins/lands of all FSB agents.
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
Input
VCC are the power lands for the processor. The voltage supplied to
these lands is determined by the VID[5:0] lands.
Input VCCA provides isolated power for the internal processor core PLLs.
Input VCCIOPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSE is an isolated low impedance connection to processor
Output core power (V_CC). It can be used to sense or measure voltage near
the silicon with little noise.
Output
This land is provided as a voltage regulator feedback sense point for
V_CC. It is connected internally in the processor package to the sense
point land U27 as described in the Voltage Regulator-Down (VRD)
10.1 Design Guide for Desktop Socket 775.
Output
VID[5:0] (Voltage ID) signals are used to support automatic
selection of power supply voltages (V_CC). Refer to the Voltage
Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775
for more information. The voltage supply for these signals must be
valid before the VR can supply V_CC to the processor. Conversely, the
VR output must be disabled until the voltage supply for the VID
signals becomes valid. The VID signals are needed to support the
processor voltage specification variations. See Table 2 for definitions
of these signals. The VR must supply the voltage that is requested
by the signals, or disable itself.
Input
VSS are the ground lands for the processor and should be connected
to the system ground plane.
Input VSSA is the isolated ground for internal PLLs.
VSS_SENSE is an isolated low impedance connection to processor
Output core V_SS. It can be used to sense or measure ground near the silicon
with little noise.
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Datasheet