3XX Datasheet, PDF (71/82 Pages) Intel Corporation – Celeron D Processor

Features
6.2.3
6.2.4
Stop-Grant State—State 3
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.
Since the GTL+ signal pins receive power from the FSB, these pins should not be driven (allowing
the level to return to V_CC) for minimum power drawn by the termination resistors in this state. In
addition, all other input pins on the FSB should be driven to the inactive state.
BINIT# will not be serviced while the processor is in the Stop-Grant state. The event is latched and
can be serviced by software upon exit from the Stop Grant state.
RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop-
Grant state. A transition back to the Normal state will occur with the de-assertion of the STPCLK#
signal. When re-entering the Stop Grant state from the Sleep state, STPCLK# should only be de-
asserted one or more bus clocks after the de-assertion of SLP#.
A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the FSB
(see Section 6.2.4). A transition to the Sleep state (see Section 6.2.5) occurs with the assertion of
the SLP# signal.
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] are latched by the processor,
and only serviced when the processor returns to the Normal state. Only one occurrence of each
event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor processes snoops on the FSB and latches interrupts
delivered on the FSB.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is asserted if there
is any pending interrupt latched within the processor. Pending interrupts that are blocked by the
EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to
system logic that it should return the processor to the Normal state.
HALT/Grant Snoop State—State 4
The processor responds to snoop or interrupt transactions on the FSB while in Stop-Grant state or
in AutoHALT Power Down state. During a snoop or interrupt transaction, the processor enters the
HALT/Grant Snoop state. The processor stays in this state until the snoop on the FSB has been
serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched.
After the snoop is serviced or the interrupt is latched, the processor returns to the Stop-Grant state
or AutoHALT Power Down state, as appropriate.
Datasheet
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