3XX Datasheet, PDF (26/82 Pages) Intel Corporation – Celeron D Processor

Electrical Specifications
Table 2-10. GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit Notes¹
V_IL
Input Low Voltage
V_IH
Input High Voltage
V_OH
Output High Voltage
0.0
GTLREF + (0.10 * V_CC)
0.90*V_CC
GTLREF – (0.10 * V_CC)
V_CC
V_CC
V
2,3
V
3,4,5
V
3,5
I_OL
Output Low Current
I_LI
I_LO
R_{on_compatible}
R_{on_optimized}
Input Leakage Current
Output Leakage Current
Buffer On Resistance
Buffer On Resistance
N/A
N/A
N/A
6.33
8
V_CC/
[0.50*RR_{TT_MIN}+R_{ON_MIN}]
A
± 200
µA
6
± 200
µA
7
10.33
Ω
8
12
Ω
8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V_IL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. The V_CC referred to in these specifications is the instantaneous V_CC.
4. V_IH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. V_IH and V_OH may experience excursions above V_CC.
6. Leakage to V_SS with pin held at V_CC.
7. Leakage to V_CC with pin held at 300 mV.
8. These specifications are different depending on whether the platform is forward compatible to the Celeron D proces-
sor or if it is optimized for the Celeron D processor. A compatible platform is one that is designed for a previous gen-
eration processor but has some level of compatibility with the Celeron D processor. An optimized platform is one
designed specifically for the Celeron D processor; however, it may have some level of compatibility with previous
generation processors.
Table 2-11. Asynchronous GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit Notes¹
V_IL
Input Low Voltage
0.0
V_CC/2 – (0.10 * V_CC)
V
V_IH
Input High Voltage
V_CC/2 + (0.10 * V_CC)
V_CC
V
V_OH
Output High Voltage
0.90*V_CC
V_CC
V
I_OL
Output Low Current
—
V_CC/[0.50*R_{TT_MIN}+R_{ON_MIN}] A
I_IL
Input Leakage Current
N/A
± 200
µA
I_LO
Output Leakage Current
N/A
± 200
µA
R_{on_compatible} Buffer On Resistance
6.33
10.33
W
R_{on_optimized} Buffer On Resistance
8
12
W
2,3
3,4,5,6
5,6,7
8
9
10
11
11
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V_IL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals
V_IH = GTLREF + (0.10 * V_CC) and V_IL= GTLREF – (0.10 * V_CC).
4. V_IH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. V_IH and V_OH may experience excursions above V_CC.
6. The V_CC referred to in these specifications refers to instantaneous V_CC.
7. All outputs are open drain.
8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.
9. Leakage to V_SS with pin held at V_CC.
10. Leakage to V_CC with pin held at 300 mV.
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Datasheet